JPS583260A - Vertical type buried capacitor - Google Patents
Vertical type buried capacitorInfo
- Publication number
- JPS583260A JPS583260A JP56101112A JP10111281A JPS583260A JP S583260 A JPS583260 A JP S583260A JP 56101112 A JP56101112 A JP 56101112A JP 10111281 A JP10111281 A JP 10111281A JP S583260 A JPS583260 A JP S583260A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- capacitor
- dielectric
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置における竪型埋め込みキャパシタに
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical buried capacitor in a semiconductor device.
半導体装置を構成する素子は能動素子と受動素子とから
なることは周知であるが、受動素子は主として抵抗とキ
ャパシタとである。これらの受動素子は構造的には簡易
であるが半導体層の表面において大きな表面積を必要と
し、集積度を向上するための隘路となっていた。It is well known that elements constituting a semiconductor device are composed of active elements and passive elements, and the passive elements are mainly resistors and capacitors. Although these passive elements are simple in structure, they require a large surface area on the surface of the semiconductor layer, which has been a bottleneck in improving the degree of integration.
従来技術においては、抵抗もキャパシタも半導体層上に
平面的に配置されてい−たが、これを立体的に配置する
ことができれば、集積度向上のために極めて有効である
ことは自明であった。ところが、（イ）半導体層中に、
幅が狭く深さの深い溝状開口を正確に形成することが必
らずしも容易でなかったこと、（ロ）かかる溝状開口に
導体特に金属層を形成することが必らずしも容易でなか
ったこと等の理由により、竪型の埋め込みキャパシタは
未だ実現されるに至っていなかった。In conventional technology, both resistors and capacitors were arranged flatly on a semiconductor layer, but it was obvious that if they could be arranged three-dimensionally, it would be extremely effective for increasing the degree of integration. . However, (a) in the semiconductor layer,
(b) It is not always easy to accurately form a narrow and deep groove-like opening, and (b) it is not always easy to form a conductor, especially a metal layer, in such a groove-like opening. A vertical buried capacitor has not yet been realized because it was not easy to do so.
そこで、本特許出願の発明者等は、かかる要請にこれえ
るものとして、半導体装置における竪型埋め込みキャパ
シタとその製造方法とに係る発明を完成した。Therefore, the inventors of the present patent application have completed an invention relating to a vertical buried capacitor in a semiconductor device and a method for manufacturing the same in order to meet such demands.
その構造の要旨は、半導体層の表面から半導体層中に幅
の狭い例えば５μＩｎ程度の幅を有し、深さの深い例え
ば５μｍｎ程度の深さを有する溝状の開口を形成し、こ
の開口の表面と上記の半導体層表面の少なくともキャパ
シタ形成予定領域上とには半導体酸化物等の誘電体より
なる層が形成されており、この開口の表面と上記の半導
体層表面のキャパシタ形成予定領域とに形成された上記
の誘電体よりなる層の上には導体層例えば金属層が形成
されており、この導体層をもってキャパシタの一方の電
極を構成することにある。この構造を可能にした主たる
理由は以下に述べる製造方法の発明にあるが、この構造
の特徴が以下に述べる製造方法を構成する各工程の組み
合わせから決定されたことも明らかである。The gist of the structure is to form a groove-shaped opening in the semiconductor layer from the surface of the semiconductor layer, which has a narrow width of about 5 μIn and a deep depth of about 5 μm, for example. A layer made of a dielectric material such as a semiconductor oxide is formed on the surface of the opening and at least on the region where the capacitor is to be formed on the surface of the semiconductor layer. A conductor layer, such as a metal layer, is formed on the formed dielectric layer, and this conductor layer constitutes one electrode of the capacitor. The main reason for making this structure possible is the invention of the manufacturing method described below, but it is also clear that the characteristics of this structure were determined from the combination of the respective steps constituting the manufacturing method described below.
ここで、牛ヤパシタンスの値ｃが、 但し、ｄは電極間距離であり、 Ｓは対向する電極面積であり、 ６は対向する電極間に介在する誘電体 の誘電率である。Here, the value c of cow yapacitance is However, d is the distance between the electrodes, S is the area of the opposing electrodes, 6 is a dielectric material interposed between opposing electrodes is the dielectric constant of
であることは周知であるから、誘電体すなわち半導体酸
化物、半導体窒化物等の厚さは絶縁耐力が許すかぎり薄
いことが望ましい。半導体装置の受けるサージ電圧がＩ
ＯＶ程度である場合、理論的には誘電体の厚さは２５ｏ
Ｘ程度で十分な筈であるが、実際には２５０Ｘ以下では
絶縁耐力が不安定であるため、５００Ａあるいはそれ以
上の値がよ（選ばれる。It is well known that the thickness of the dielectric material, ie, semiconductor oxide, semiconductor nitride, etc., is as thin as the dielectric strength allows. The surge voltage that the semiconductor device receives is I
If it is about OV, the theoretical thickness of the dielectric is 25o.
A value of about X should be sufficient, but in reality the dielectric strength is unstable below 250X, so a value of 500A or more is preferred.
次に、その製造方法の要旨は、（イ）高電流密度・高加
速エネルギーをもってなす垂直性イオンビームエツチン
グ法を使用して半導体層の表面から半導体層中の幅の狭
い例えば５μｍ０程度の輻を有し、深さの深い例えば５
μＩｒｌ程度の深さを有する溝状の開口を形成し、（ロ
）その後、このエツチング工程に使用したマスクを除去
し表面を熱酸化し、（ハ）更憾、その後、この半導体基
板を弗酸（ＨＦ）系洗浄液をもって洗浄して上記の開口
の表面と上記の半導体層表面の少なくともキャパシタ形
成予定領域とを洗浄して異物を除去し、（ニ）この半導
体基板を酸化して上記の開口の表面と上記の半導体層表
面の少な（とむキャパシタ形成予定領域に半導体酸化膜
等の誘電体層を少なくとも２５０ Ｘ程度の厚さに形成
し、（ホ）無電解メッキ法を使用してニッケル（Ｎｉ
）等の導体よりなる薄層を上記の誘電体層上に形成し、
（へ）この導体よりなる薄層上に更にアル４ニユウＡ
（ＡＩ）等の導体よりなる層を形成し。Next, the gist of the manufacturing method is as follows. and the depth is deep e.g. 5
A groove-like opening having a depth of approximately μIrl is formed, (b) the mask used in this etching step is removed and the surface is thermally oxidized, and (c) this semiconductor substrate is etched with hydrofluoric acid. (HF)-based cleaning solution is used to clean the surface of the opening and at least the area where the capacitor is to be formed on the surface of the semiconductor layer to remove foreign substances; (d) oxidize the semiconductor substrate to clean the surface of the opening A dielectric layer such as a semiconductor oxide film is formed to a thickness of at least 250× on the surface and a small area of the surface of the semiconductor layer where a capacitor is to be formed, and (e) a nickel (Ni) layer is formed using an electroless plating method.
) is formed on the above dielectric layer,
(f) Further Al 4 New A on the thin layer made of this conductor
A layer made of a conductor such as (AI) is formed.
（ト）この導体よりなる層をもつてキャパシタの一方の
電極を構成することにある。他方の電極は半導体基板で
ある。(g) The layer made of this conductor constitutes one electrode of the capacitor. The other electrode is a semiconductor substrate.
ここで、高エネルギーをもってなすイオンビームエツチ
ング法は１〜１（）Ｋｅ Ｖ程度のエネルギーをもって
アルゴンイオン（Ａｒ”）を使用しても、又、四弗化炭
素（ｃｉ；”４）を反応性イオン源物質として質量分離
器を通さずとも、あるいは通して特定の弗化炭素系イオ
ン（ＣＦ３”、ＣＦ２＋など）を選び、５００ｅＶ程度
のエネルギーをもってなしても可能である。ここで使用
するマスクは、たとえば２０μｍｎ程度の厚さを有する
金属や金属酸化物のマスクでも、表面に付着・あるいは
形成させた半導体酸化物等のマスクでも可能である。こ
こでシリコン酸化物（５ｉ（）ｚ）をマスクとし、弗化
炭素系イオンを照射する場合、塩素雰囲気で行うと高い
効率でエッチできることが判っている。開口形成後の洗
浄工程は、薄い誘電体層をもって高い絶縁耐力と大きな
キャパシタンスを得るために必須である。又、ニッケル
（Ｎｉ ）等の無電解メッキ工程も、このように幅の狭
い電気的に不導体である誘電体溝内に導電層を形成する
工程として必須である。Here, the ion beam etching method performed with high energy uses argon ions (Ar") with an energy of about 1 to 1 () Ke V, or carbon tetrafluoride (ci; "4) It is possible to perform the ionization without passing through a mass separator as the ion source material, or by selecting specific fluorocarbon ions (CF3'', CF2+, etc.) and using an energy of about 500 eV.The mask used here is For example, it is possible to use a mask made of metal or metal oxide with a thickness of about 20 μm, or a mask made of semiconductor oxide attached or formed on the surface.Here, silicon oxide (5i()z) is used as a mask. It is known that when irradiating with carbon fluoride ions, etching can be performed with high efficiency in a chlorine atmosphere.The cleaning process after the opening is performed in order to obtain high dielectric strength and large capacitance with a thin dielectric layer. Further, an electroless plating process such as nickel (Ni 2 ) is also essential as a process for forming a conductive layer in such a narrow dielectric groove, which is an electrically nonconducting material.
ところが、この発明にあっては、キャパシタの一方の１
に極がシリコン（Ｓｔ ）基板そのものであるため、蓄
積層形成と反対の極性、すなわち空乏層形成の極性で用
いられるときこのシリコン（８ｉ ）基板中に空乏層が
伸延し、実質的に電極間距離が増大したと同一の結果と
なり、得られるキャパシタンスの値が非常に減少する欠
点がある。However, in this invention, one of the capacitors
Since the electrode is the silicon (St) substrate itself, when it is used with the opposite polarity to the formation of the accumulation layer, that is, the polarity of the formation of the depletion layer, the depletion layer extends into this silicon (8i) substrate, and there is a substantial gap between the electrodes. As the distance increases, the result is the same, with the disadvantage that the value of the capacitance obtained is greatly reduced.
本発明の目的は、この欠点を解消することにあり、半導
体層の表面から半・導体層中に幅の狭い溝状の開口を形
成し、この開口の表面と上記の半導体層表面の少なくと
もキャパシタ形成予定領域上とに半導体酸化物、半導体
窒化物等の絶縁物層を形成した後、上記の溝状開口の表
面と半導体層表面の少なくともキャパシタ形成予定領域
上とにタンタル（Ｔａ ）等よりなる第１の金属薄層を
形成し、その上に酸化タンタル（Ｔａ２ｕｓ ）等の誘
電体層を形成シ、更にその上にアルミニュウム（ＡＩ）
・タンタル（Ｔａ）等よりなる第２の金属層を形成し
、第１の金属薄層と誘電体層と第２の金属層とをもって
キャパシタを構成することにある。An object of the present invention is to eliminate this drawback by forming a narrow groove-like opening in the semiconductor layer from the surface of the semiconductor layer, and connecting at least a capacitor between the surface of the opening and the surface of the semiconductor layer. After forming an insulating layer of semiconductor oxide, semiconductor nitride, etc. on the region where the capacitor is to be formed, a layer of tantalum (Ta) or the like is formed on the surface of the groove-shaped opening and at least on the region where the capacitor is to be formed on the surface of the semiconductor layer. A first metal thin layer is formed, a dielectric layer such as tantalum oxide (Ta2us) is formed on it, and then aluminum (AI) is formed on it.
- A second metal layer made of tantalum (Ta) or the like is formed, and the first thin metal layer, dielectric layer, and second metal layer constitute a capacitor.
ここで、第１の金属薄層としてタンタル（Ｔａ ）を１
例として挙げた理由は、これを酸化して形成しうる酸化
タンタル（’ｒａ２ｏ５ ）の誘電率が大であるためで
あり、しかも、このタンタル酸化１、物が金属酸化物の
中ではとりわけ優れた絶縁性と安定性を有するからであ
る。Here, tantalum (Ta) is used as the first metal thin layer at 1
The reason for using this as an example is that tantalum oxide ('ra2o5), which can be formed by oxidizing it, has a high dielectric constant. This is because it has insulation properties and stability.
以下、図面を参照しつつ、本発明の一実施例に係る。半
導体装置における竪型埋め込みキャパシタの製造方法の
各主要工程を説明し、本発明の構成と特有の効果とを明
らかにする。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each main process of a method for manufacturing a vertical buried capacitor in a semiconductor device will be explained, and the structure and unique effects of the present invention will be clarified.
第１図参照
シリコン（８ｉ）基板１の表面を熱酸化して厚さ１４ｍ
０程度の二酸化シリコン（Ｓｉ００層２を形成し、この
上にレジスト層３を塗布した後、リソグラフィー法を使
用してこれら２層を選択的にエッチしてマスクを形成す
る。このマスクを使用して四弗化炭素（ＣＦ４ ）と塩
素（ｅｌｚ）とを１００ ：５０に含有する雰囲気中で
イオンを０．１〜ＩＫＶの電圧をもって加速して照射し
てイオンビームエツチングを施し、開口４を形成する。Refer to Figure 1. The surface of silicon (8i) substrate 1 is thermally oxidized to a thickness of 14 m.
After forming a silicon dioxide (Si00) layer 2 of about 0.0 and applying a resist layer 3 on top of this, a lithography method is used to selectively etch these two layers to form a mask. Then, in an atmosphere containing carbon tetrafluoride (CF4) and chlorine (ELZ) at a ratio of 100:50, ions are accelerated and irradiated with a voltage of 0.1 to IKV to perform ion beam etching to form the opening 4. do.
第２図参照
上記のエツチング工程に使用したマスクを、残存レジス
ト層は酸素プラズマアッシング法で、５ｉＯｚ層は弗酸
（ＨＦ）＋こよって、夫々除去した後、とのンＩＪコン
（Ｓｌ）基板１を１． ｏｏｏ ｅ程度の酸素（０２）
中に２時間曝す等の方法により酸化し、上記の開口４の
表面とシリコン（Ｓｉ）基板１の表面とに絶縁物層５を
形成する。この絶縁物層５の厚さは絶縁性と基板間、容
量の形成の２つの意味で５００〜１．０００Ａ程度が望
ましい。Refer to Figure 2. After removing the mask used in the above etching process, the remaining resist layer was removed by oxygen plasma ashing, and the 5iOz layer was removed using hydrofluoric acid (HF). 1 to 1. ooo e level of oxygen (02)
The insulating material layer 5 is formed on the surface of the opening 4 and the surface of the silicon (Si) substrate 1 by oxidizing the silicon substrate 1 by exposing it to the inside for 2 hours or the like. The thickness of this insulating layer 5 is desirably about 500 to 1.000 A from the viewpoint of insulation and formation of capacitance between substrates.
第３図参照
ツツイて、上記の絶縁物層５上に、タンタル（Ｔａ）の
ハロゲン化物を反応ガスとして有機金属化学気相反応法
（ＭＯＣＶＤ法）を使用してタンｐ ル（Ｔａ）等の層
６を形成する。このタンタル（Ｔａ）等の層７の厚さは
１μｍ程度で十分である。本ＭＯＣＶ Ｄ法はカバレッ
ヂを良くする為減圧下で行うＯ
つづいて、タンタル（Ｔａ）等の層６を弗酸・硝酸系溶
液でその表面を軽く洗浄し、硝酸（ＨＮＯ３）溶液中で
１００ Ｖ程度の電圧で陽極酸化して、酸化タンタル（
’ｐａｚＱｓ）等よりなる層７を形成する。Referring to FIG. 3, tantalum (Ta), etc., is deposited on the insulating layer 5 using a metal organic chemical vapor phase reaction method (MOCVD method) using a tantalum (Ta) halide as a reaction gas. Form layer 6. A thickness of about 1 μm is sufficient for the layer 7 made of tantalum (Ta) or the like. This MOCV D method is performed under reduced pressure to improve coverage.Next, the surface of the layer 6 made of tantalum (Ta), etc. is lightly cleaned with a hydrofluoric acid/nitric acid solution, and then heated at 100 V in a nitric acid (HNO3) solution. Tantalum oxide (
'pazQs) or the like is formed.
酸化タンタル（Ｔａ ２ Ｕｓ ）等よりなる層７はキ
ャパシタの誘電体として機能するので５００Ａ程度の厚
さにする。The layer 7 made of tantalum oxide (Ta 2 Us) or the like functions as a dielectric of the capacitor, and is therefore made to have a thickness of about 500 Å.
第４図参照
次に、無電解メッキ法を使用してニッケル（Ｎｉ ）等
の薄層８を形成した後、電解メッキ法でアルミニュウム
（Ａ１）等の層９を形成する。このＮ９の厚さは必要と
する抵抗値によって決定される。また必要に応じてカバ
ー膜１０を化学気相反応法でつける。Refer to FIG. 4 Next, a thin layer 8 of nickel (Ni) or the like is formed using an electroless plating method, and then a layer 9 of aluminum (A1) or the like is formed using an electrolytic plating method. The thickness of this N9 is determined by the required resistance value. Further, if necessary, a cover film 10 is applied by a chemical vapor phase reaction method.
以上の工程によって、２層の゛−金属層すなわちタンタ
ル（Ｔａ）層とアルミニュウム（Ａｔ）層とその間に挟
まれる誘電体層すなわち酸化タンタル（’ｒａ ２ Ｑ
６ ）層とによってキャパシタが形成される。Through the above steps, two metal layers, namely a tantalum (Ta) layer and an aluminum (At) layer, and a dielectric layer sandwiched between them, namely tantalum oxide ('ra 2 Q) are formed.
6) A capacitor is formed by the layers.
第５図参照
本発明の一実施例に係る、半導体装置における竪型埋め
込みキャパシタを含み電界効果型トランジスタをセル選
択素子とする記憶素子の断面図を１例として第５図に示
す。図において、１１はシリコン（Ｓｉ）基板であり、
１２はソース１ドレイン領域であり、１３はゲート絶縁
膜であり、１４はゲートでありこの例においてはワード
ラインを構成し、１５はソース用アルミニュウム（ＡＩ
）［極であり、この例においてはビットラインを構成し
、１６はゲート１４とドレイン−ソース１２との間の絶
縁物である。１７か本発明に係るキャパシタ領域の絶縁
物層であり、１８が本発明に係るキャパシタの一方の電
極（タンタル）であり、１９が本発明に係るキャｐ４シ
タの誘電体層（酸化タンタルＴａ２０ｓ）であり、２０
が本発明に係る牛ヤパシタの他方の電極（アルミニュウ
ム）である。Refer to FIG. 5 FIG. 5 shows, as an example, a cross-sectional view of a memory element in a semiconductor device according to an embodiment of the present invention, which includes a vertical buried capacitor and uses a field effect transistor as a cell selection element. In the figure, 11 is a silicon (Si) substrate,
12 is a source 1 drain region, 13 is a gate insulating film, 14 is a gate which constitutes a word line in this example, and 15 is an aluminum (AI) for the source.
) [pole, which in this example constitutes the bit line, 16 is the insulator between the gate 14 and the drain-source 12. 17 is an insulating layer of the capacitor region according to the present invention, 18 is one electrode (tantalum) of the capacitor according to the present invention, and 19 is a dielectric layer (tantalum oxide Ta20s) of the capacitor according to the present invention. and 20
is the other electrode (aluminum) of the bovine yapacita according to the present invention.
図から明らかなように、キャパシタの占める半導体基板
１１の面積はキャパシタが平面的に形成されている従来
技術における記憶素子におけるよりも同一容量値ではは
るかに少ないばかりでなく、酸化タンタル（Ｔａｇ’ｓ
）よりなる誘電体の厚さは５００Ａ程度でも誘電率が
大きいのでキャパシタンス値の大きなキャパシタとなっ
ている。As is clear from the figure, the area of the semiconductor substrate 11 occupied by the capacitor is not only much smaller for the same capacitance value than in the conventional memory element in which the capacitor is formed in a planar manner, but also
) has a large dielectric constant even if the thickness is about 500 A, resulting in a capacitor with a large capacitance value.
以上説明せるとおり、本発明によれば、キャパシタが半
導体基板内に立体的に形成されているため平面積当りの
キャパシタ表面積が増大しており、しかも、誘電体の誘
電率が極めて大きいのでキャパシタンス値の大きな、半
導体装置における竪型埋め込みキャパシタを提供するこ
とができる。As explained above, according to the present invention, since the capacitor is three-dimensionally formed within the semiconductor substrate, the surface area of the capacitor per plane area is increased, and since the dielectric constant of the dielectric material is extremely large, the capacitance value is increased. It is possible to provide a vertical buried capacitor in a semiconductor device with a large size.
第１．２．３．４図は、本発明の一実施例に係る、半導
体装置における竪型埋め込みキャパシタの製造方法にお
ける主要工程を示す基板断面図である。第５図は本発明
の一実施例に係る、半導体装置における竪型埋め込みキ
ャパシタを含み電界効果トランジスタをドライバとする
記憶素子の断ｉ、ｎ、、−半導体基板、２・・・二酸化
シリコン層（マスク）、３・・脅レジスト、４−＠・開
口、５゜１７・・・絶縁物層（二酸化シリコン層）、６
．１８・・・一方の電極（タンタル）、７．１９・・・
誘電体層（酸化タンタル）、８，９，２０・昏・他方の
電極、１０・・・カバー膜、１２・・ｅソース・ドレイ
ン領域、１３・・・ゲート絶縁膜、１４・・・ゲート（
ワードライン） 、１５・・・ソース電極（ビ・ノドラ
イン）、１６・・・層間絶縁物。
代理人 弁理士 松岡宏四暗−′、力1.2.3.4 is a cross-sectional view of a substrate showing main steps in a method for manufacturing a vertical buried capacitor in a semiconductor device according to an embodiment of the present invention. FIG. 5 shows cross sections of a memory element including a vertical buried capacitor and using a field effect transistor as a driver in a semiconductor device according to an embodiment of the present invention. Mask), 3... Threat resist, 4-@- Opening, 5゜17... Insulator layer (silicon dioxide layer), 6
．． 18...One electrode (tantalum), 7.19...
Dielectric layer (tantalum oxide), 8, 9, 20 - other electrode, 10 - cover film, 12 - e source/drain region, 13 - gate insulating film, 14 - gate (
word line), 15... source electrode (bi-nod line), 16... interlayer insulator. Agent: Patent Attorney Hiroshi Matsuoka-', Chikara
Claims (1)
が形成され、該開口表面と前記半導体層表面の少なくと
もキャパシタ形成領域上とに絶縁物層が形成され、前記
開口表面と前記半導体層表面のキャパシタ形成領域上と
に形成された絶縁物上に第１の導体層が形成され、該導
体層上に誘電体層が形成され、該誘電体層上に第２の導
体層が形成されており、前記第１の導体層と前記誘電体
層と前記第２の導体層とをもって前記キャパシタが構成
されていることを特徴とする竪型埋め込みキャパシタ。A narrow groove-shaped opening is formed in the semiconductor layer from the surface of the semiconductor layer, an insulating layer is formed on the opening surface and at least a capacitor formation region on the semiconductor layer surface, and an insulating material layer is formed between the opening surface and the semiconductor layer. A first conductor layer is formed on the insulator formed on the capacitor formation region on the layer surface, a dielectric layer is formed on the conductor layer, and a second conductor layer is formed on the dielectric layer. A vertical buried capacitor, characterized in that the capacitor is constituted by the first conductor layer, the dielectric layer, and the second conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101112A JPS583260A (en) | 1981-06-29 | 1981-06-29 | Vertical type buried capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101112A JPS583260A (en) | 1981-06-29 | 1981-06-29 | Vertical type buried capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS583260A true JPS583260A (en) | 1983-01-10 |
| JPH0145232B2 JPH0145232B2 (en) | 1989-10-03 |
Family
ID=14291985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56101112A Granted JPS583260A (en) | 1981-06-29 | 1981-06-29 | Vertical type buried capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583260A (en) |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213460A (en) * | 1982-06-07 | 1983-12-12 | Nec Corp | Semiconductor integrated circuit device |
| JPS5982761A (en) * | 1982-11-04 | 1984-05-12 | Hitachi Ltd | Semiconductor memory |
| FR2544537A1 (en) * | 1983-04-15 | 1984-10-19 | Hitachi Ltd | SEMICONDUCTOR MEMORY DEVICE OF DYNAMIC MEMORY TYPE WITH DIRECT OR RANDOM ACCESS (DRAM) WITH HIGH INTEGRATION DENSITY AND METHOD OF MANUFACTURING SUCH A DEVICE |
| JPS59191374A (en) * | 1983-04-15 | 1984-10-30 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS6065559A (en) * | 1983-09-21 | 1985-04-15 | Hitachi Ltd | Semiconductor memory |
| FR2554954A1 (en) * | 1983-11-11 | 1985-05-17 | Hitachi Ltd | SEMICONDUCTOR MEMORY DEVICE |
| JPS6092658A (en) * | 1983-10-27 | 1985-05-24 | Matsushita Electronics Corp | Semiconductor memory device |
| EP0145606A2 (en) * | 1983-12-13 | 1985-06-19 | Fujitsu Limited | Semiconductor memory device |
| JPS60113460A (en) * | 1983-11-25 | 1985-06-19 | Oki Electric Ind Co Ltd | Dynamic memory element |
| JPS60198771A (en) * | 1984-03-23 | 1985-10-08 | Hitachi Ltd | Semiconductor device |
| JPS60200565A (en) * | 1984-03-26 | 1985-10-11 | Hitachi Ltd | Semiconductor device |
| JPS6136965A (en) * | 1984-07-30 | 1986-02-21 | Toshiba Corp | Semiconductor memory device |
| JPS6167955A (en) * | 1984-09-11 | 1986-04-08 | Fujitsu Ltd | Semiconductor memory device and manufacture thereof |
| JPS6190395A (en) * | 1984-10-09 | 1986-05-08 | Fujitsu Ltd | Semiconductor memory cell |
| JPS61160969A (en) * | 1984-12-07 | 1986-07-21 | テキサス インスツルメンツ インコ−ポレイテツド | Memory cell and manufacture thereof |
| JPS61207055A (en) * | 1985-03-11 | 1986-09-13 | Nec Corp | Semiconductor memory device |
| JPS627154A (en) * | 1985-07-02 | 1987-01-14 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6237366U (en) * | 1985-08-14 | 1987-03-05 | ||
| US4717942A (en) * | 1983-07-29 | 1988-01-05 | Nec Corporation | Dynamic ram with capacitor groove surrounding switching transistor |
| US4792834A (en) * | 1984-01-20 | 1988-12-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device with buried layer under groove capacitor |
| US4999689A (en) * | 1987-11-06 | 1991-03-12 | Sharp Kabushiki Kaisha | Semiconductor memory |
| US5012308A (en) * | 1984-08-27 | 1991-04-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US5214496A (en) * | 1982-11-04 | 1993-05-25 | Hitachi, Ltd. | Semiconductor memory |
| CN107437538A (en) * | 2016-05-26 | 2017-12-05 | 台湾积体电路制造股份有限公司 | Integrated circuit, vertical metal insulator metal capacitor and its manufacture method |
-
1981
- 1981-06-29 JP JP56101112A patent/JPS583260A/en active Granted
Cited By (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213460A (en) * | 1982-06-07 | 1983-12-12 | Nec Corp | Semiconductor integrated circuit device |
| JPH0342514B2 (en) * | 1982-11-04 | 1991-06-27 | ||
| JPS5982761A (en) * | 1982-11-04 | 1984-05-12 | Hitachi Ltd | Semiconductor memory |
| US5214496A (en) * | 1982-11-04 | 1993-05-25 | Hitachi, Ltd. | Semiconductor memory |
| FR2544537A1 (en) * | 1983-04-15 | 1984-10-19 | Hitachi Ltd | SEMICONDUCTOR MEMORY DEVICE OF DYNAMIC MEMORY TYPE WITH DIRECT OR RANDOM ACCESS (DRAM) WITH HIGH INTEGRATION DENSITY AND METHOD OF MANUFACTURING SUCH A DEVICE |
| JPS59191373A (en) * | 1983-04-15 | 1984-10-30 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS59191374A (en) * | 1983-04-15 | 1984-10-30 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH0576785B2 (en) * | 1983-04-15 | 1993-10-25 | Hitachi Ltd | |
| US5021842A (en) * | 1983-04-15 | 1991-06-04 | Hitachi, Ltd. | Trench DRAM cell with different insulator thicknesses |
| US4717942A (en) * | 1983-07-29 | 1988-01-05 | Nec Corporation | Dynamic ram with capacitor groove surrounding switching transistor |
| JPS6065559A (en) * | 1983-09-21 | 1985-04-15 | Hitachi Ltd | Semiconductor memory |
| JPS6092658A (en) * | 1983-10-27 | 1985-05-24 | Matsushita Electronics Corp | Semiconductor memory device |
| FR2554954A1 (en) * | 1983-11-11 | 1985-05-17 | Hitachi Ltd | SEMICONDUCTOR MEMORY DEVICE |
| JPH0347588B2 (en) * | 1983-11-25 | 1991-07-19 | Oki Electric Ind Co Ltd | |
| JPS60113460A (en) * | 1983-11-25 | 1985-06-19 | Oki Electric Ind Co Ltd | Dynamic memory element |
| JPS60126861A (en) * | 1983-12-13 | 1985-07-06 | Fujitsu Ltd | Semiconductor memory device |
| JPH0562468B2 (en) * | 1983-12-13 | 1993-09-08 | Fujitsu Ltd | |
| US4646118A (en) * | 1983-12-13 | 1987-02-24 | Fujitsu Limited | Semiconductor memory device |
| EP0145606A2 (en) * | 1983-12-13 | 1985-06-19 | Fujitsu Limited | Semiconductor memory device |
| US4792834A (en) * | 1984-01-20 | 1988-12-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device with buried layer under groove capacitor |
| JPS60198771A (en) * | 1984-03-23 | 1985-10-08 | Hitachi Ltd | Semiconductor device |
| JPS60200565A (en) * | 1984-03-26 | 1985-10-11 | Hitachi Ltd | Semiconductor device |
| JPS6136965A (en) * | 1984-07-30 | 1986-02-21 | Toshiba Corp | Semiconductor memory device |
| US5012308A (en) * | 1984-08-27 | 1991-04-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| JPH0365904B2 (en) * | 1984-09-11 | 1991-10-15 | ||
| JPS6167955A (en) * | 1984-09-11 | 1986-04-08 | Fujitsu Ltd | Semiconductor memory device and manufacture thereof |
| JPH0542758B2 (en) * | 1984-10-09 | 1993-06-29 | Fujitsu Ltd | |
| JPS6190395A (en) * | 1984-10-09 | 1986-05-08 | Fujitsu Ltd | Semiconductor memory cell |
| JPS61160969A (en) * | 1984-12-07 | 1986-07-21 | テキサス インスツルメンツ インコ−ポレイテツド | Memory cell and manufacture thereof |
| JPS61207055A (en) * | 1985-03-11 | 1986-09-13 | Nec Corp | Semiconductor memory device |
| JPS627154A (en) * | 1985-07-02 | 1987-01-14 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6237366U (en) * | 1985-08-14 | 1987-03-05 | ||
| US4999689A (en) * | 1987-11-06 | 1991-03-12 | Sharp Kabushiki Kaisha | Semiconductor memory |
| CN107437538A (en) * | 2016-05-26 | 2017-12-05 | 台湾积体电路制造股份有限公司 | Integrated circuit, vertical metal insulator metal capacitor and its manufacture method |
| CN107437538B (en) * | 2016-05-26 | 2020-03-31 | 台湾积体电路制造股份有限公司 | Integrated circuit, vertical metal-insulator-metal capacitor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0145232B2 (en) | 1989-10-03 |
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