JPS5832421A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5832421A JPS5832421A JP56130557A JP13055781A JPS5832421A JP S5832421 A JPS5832421 A JP S5832421A JP 56130557 A JP56130557 A JP 56130557A JP 13055781 A JP13055781 A JP 13055781A JP S5832421 A JPS5832421 A JP S5832421A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- electrode
- electrodeposition
- circumference
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体クエーハのペレット領域間に刻設した
メサ溝にガラス保護膜を形成する工程を含む半導体装置
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device including a step of forming a glass protective film in a mesa groove carved between pellet regions of a semiconductor wafer.
一般に、メ?型のトランジスタやナイリスタなどの半導
体装置は、1枚の半導体ウェーハに複数の半導体ベレッ
ト領域(以下単にペレットと称す)を選択拡散等で形成
する工程、ウェーハのペレット間にメサ溝をエツチング
形成する工程、メサ溝に保護膜を被着する工程、半導体
ウェーハ表裏両面に電極を形成する工程、半導体つ・エ
ーハを各半導体ベレット毎に細分割する工程を経て製造
されている。In general, me? Semiconductor devices such as type transistors and Nyristors are manufactured through the process of forming multiple semiconductor pellet regions (hereinafter simply referred to as pellets) on a single semiconductor wafer by selective diffusion, etc., and the process of forming mesa grooves between the pellets of the wafer by etching. The semiconductor wafer is manufactured through the steps of applying a protective film to the mesa groove, forming electrodes on both the front and back surfaces of the semiconductor wafer, and dividing the semiconductor wafer into finely divided semiconductor pellets.
ところで、上記メサ溝を保鏝する保護膜は、ゴムを使用
する一合もあるが、通常はガラスを使用し、このガラス
保護膜の形成工程は、グラシペーシ曹ンと呼ばれている
。グラシペ゛←シ1ンの方法として、沈殿法、電気泳動
法、印刷法、塗布法尋があるが、この発明は電気泳動法
に係わる。□例えば、半導体装置として8CRを例にこ
のグラシペーシ■ン工程の従来の方法を説明すると、第
1図及び第2図はメサ溝形成工程が完了してグラシベー
シ冒ン工程に入るウェーハを示し、これらの図において
、N型のウェーハ1の表裏両面からP型不純物を拡散し
てP型領域2を形成し、表面側のP型領域に複数個のN
型領域をN型木綿物の選択拡散により形成して、N型領
域を含む複数のベレット領域3を形成し、その後ウェー
ハの表裏両面全域に酸化膜4を形成してから、この酸化
膜上にウェーハのベレット周上を除いて、例えばワック
ス5を塗布し、ワックス5の塗布されていないところか
ら酸化膜及びウェーハをエツチングしてウェーハのベレ
ット間メサ溝6を形成したものである。Incidentally, the protective film for protecting the mesa grooves is sometimes made of rubber, but usually glass is used, and the process of forming this glass protective film is called glazing. There are precipitation methods, electrophoresis methods, printing methods, and coating methods as methods for graphigraphy, and the present invention relates to electrophoresis methods. □For example, to explain the conventional method of the glassy pinning process using 8CR as a semiconductor device, Figures 1 and 2 show a wafer that has completed the mesa groove forming process and is undergoing the glassy baking process. In the figure, P-type impurities are diffused from both the front and back surfaces of an N-type wafer 1 to form a P-type region 2, and a plurality of N-type impurities are formed in the P-type region on the front side.
A mold region is formed by selective diffusion of an N-type cotton material to form a plurality of pellet regions 3 including the N-type region, and then an oxide film 4 is formed on the entire front and back surfaces of the wafer, and then on this oxide film. For example, wax 5 is applied to the wafer except on the circumference of the pellets, and the oxide film and the wafer are etched from the areas where the wax 5 is not applied to form mesa grooves 6 between the pellets of the wafer.
この時のメサ溝6には各ベレット領域のPN接合部が露
出し、ここに重金属、水分、ゴオ等の異物が付着すると
、リークや耐圧劣化を招くため、メサ溝6を保護する必
要がある。At this time, the PN junction of each pellet area is exposed in the mesa groove 6, and if foreign substances such as heavy metals, moisture, and goo are attached thereto, it will cause leakage and voltage resistance deterioration, so it is necessary to protect the mesa groove 6. .
即ち、まず上記クエーノ九を第3図に示すように電着液
フの中に浸漬する。この電着液は電解液にガラス微粉末
を懸濁したものである。次に、ウェーハlの表裏両面の
近傍に電極板8を配置して電極板にプラス、ウェーハに
iイナスの電圧を印加する。すると第4図に示すように
2、電着液7の中のガラス微粉末9がマイナス電位であ
るメサ#I6に電着していく。後はウェーハlを電着液
7から9を焼きしめてガラス保護膜を形成する。That is, first, the Quaeno-9 is immersed in an electrodeposition solution as shown in FIG. This electrodeposition solution is made by suspending fine glass powder in an electrolytic solution. Next, an electrode plate 8 is placed near both the front and back surfaces of the wafer l, and a positive voltage and an i-minus voltage are applied to the electrode plate and the wafer. Then, as shown in FIG. 4, the glass fine powder 9 in the electrodeposition liquid 7 is electrodeposited on the mesa #I6 which has a negative potential. After that, the wafer 1 is baked with electrodeposition liquids 7 to 9 to form a glass protective film.
ところで、このような従来のグラシペーシ1ン工程には
次の問題点があっ九。即ち、つ、エーハは周辺部にベレ
ットを形成して屯不良となる率が高く、従って、ベレッ
トはウェーハの周辺部を除く部分だけに形成されている
。そして、このウェーハのグラシペーシ嘗ンは、メサ溝
を除く全面をワックス又は酸化膜で絶縁保護して行りて
いた。第3図の状態で電圧印加するとメサ溝だけが電着
液中に露出し電着されるが、クエーイ・の周辺部と中央
部では電界の強さが均一にならず、特に、ウェーハ最外
周付近で中央部の電界との強さの差が最大となる。その
為、ガラス微粉末の層は、中央部と比較して周辺部に近
いものが大幅に厚くなる傾向がある。これが焼成後ガラ
ス厚のばらつきを生じる最大の原因である。By the way, there are the following problems with this conventional gracipaging process. That is, the wafer has a high probability of forming a pellet on the periphery and being defective, and therefore, the pellet is formed only on the portion of the wafer other than the periphery. Gracipation of this wafer was carried out by insulating and protecting the entire surface of the wafer except for the mesa groove with wax or an oxide film. When voltage is applied in the state shown in Figure 3, only the mesa grooves are exposed in the electrodeposition solution and electrodeposited, but the strength of the electric field is not uniform at the periphery and center of the wafer, especially at the outermost periphery of the wafer. The difference in strength from the electric field at the center is greatest near the center. Therefore, the layer of fine glass powder tends to be significantly thicker near the periphery than in the center. This is the biggest cause of variations in glass thickness after firing.
本発明の目的は、上記ガラス厚みのばらつきの抑制され
九半導体装置を歩留よく製造する方法を提供することで
ある。An object of the present invention is to provide a method for manufacturing semiconductor devices with high yield while suppressing the above-mentioned variations in glass thickness.
次に本発明を図面を参照して説明する。例えば第1図及
び第2図に示したウェーハをグ2シペーシ璽ンする場合
、ウェーハの周辺部の電界強度を弱める1例として、第
5図(−)、Φ)K示すような同心円状に分割した電極
18を用いればよい。電極18はステンレス製の中央円
板の周囲に直径が違う数個のステンレス条の輪体11を
放射状配置の支持棒12で支持した構造をもち、輪体1
1の間隔は周辺にゆくに従うてしだいに疎にしてあシ、
周辺部における電界の強度を中央部と等しくなるようK
しである。Next, the present invention will be explained with reference to the drawings. For example, when the wafer shown in Figures 1 and 2 is to be wrapped around the wafer, one example of weakening the electric field strength at the periphery of the wafer is to wrap it in concentric circles as shown in Figure 5 (-), Φ)K. A divided electrode 18 may be used. The electrode 18 has a structure in which several rings 11 of stainless steel strips with different diameters are supported by support rods 12 arranged radially around a central disc made of stainless steel.
The spacing of 1 becomes gradually sparser towards the periphery,
K to make the electric field strength at the periphery equal to that at the center.
It is.
これを第6図に示すように、全体を電着液7の中に浸漬
する。そして電極18にプラス、ウェーハIKマイナス
の電圧を印加する。すると電着液7の中のガラス微粉末
が露出し九メサ溝に電着していく。As shown in FIG. 6, the entire structure is immersed in an electrodeposition liquid 7. Then, a positive voltage and a negative voltage of the wafer IK are applied to the electrode 18. Then, the fine glass powder in the electrodeposition liquid 7 is exposed and electrodeposited in the nine mesa grooves.
従来の平板電極は周辺部の電界が強く、大幅に厚くガラ
ス微粉末が電着していたが、上記電極18を用いれば、
周辺部の電界社中央部と等しくなシ均一な電着が可能に
なる。Conventional flat plate electrodes have a strong electric field at the periphery and the fine glass powder is electrodeposited significantly thicker, but with the electrode 18 described above,
It is possible to achieve uniform electrodeposition in the peripheral area, which is equal to that in the central area.
以上説明したように、本発明によれば、ガラス電着時に
平板電極を用いていた場合、どおしても周辺部に電界が
集中しガラス厚みが均一でなかったものが、前記電極を
用いる事によ)、メサ溝のガラス電着層の厚さが全体に
わたつて均一化し、常に良好なグラシベーシlンが可能
とな・シ、製品の良品率の向上が図れる。As explained above, according to the present invention, when a flat plate electrode is used during glass electrodeposition, the electric field is concentrated in the peripheral area and the glass thickness is not uniform. 2) The thickness of the glass electrodeposited layer in the mesa groove is made uniform over the entire area, making it possible to always achieve good glass basing and improving the yield rate of products.
第1図は半導体ウェーへの平面図、第2図は第1図の一
部拡大断面図、第3図ば従来のグラシベーシlン工程を
説明するガラス電着装置の概略断面図、第4図は第3図
の一部拡大断面図、第5図(a)、Φ)は本発明の一実
施例に係わる電極の概略平面図とそのA−A断面図、第
6図は第5図の部品を用いたガラス電着装置の概略断面
図である。
l・−・−・半導体ウェーハ、2=、−p型領域、3・
・・・−・ベレット領域、4・・・・・・酸化膜、5・
−・−ワックス、6・−・・・・メサ溝、7−・・・・
電着液、8,18−・・・−電極、9−・・・・・ガラ
ス粉末、10−−−−−・中央円板、11・・・・−輪
体、12−・・・・支持棒。
第3回
第6 図Fig. 1 is a plan view of a semiconductor wafer, Fig. 2 is a partially enlarged sectional view of Fig. 1, Fig. 3 is a schematic sectional view of a glass electrodeposition apparatus explaining the conventional glassy basin process, and Fig. 4 is a partially enlarged cross-sectional view of FIG. 3, FIG. 1 is a schematic cross-sectional view of a glass electrodeposition apparatus using parts. l・−・−・Semiconductor wafer, 2=, −p type region, 3・
...--Bellet region, 4... Oxide film, 5.
−・−Wax, 6・−・・・・Mesa groove, 7−・・・・
Electrodeposition liquid, 8, 18--electrode, 9--glass powder, 10--center disk, 11--circular body, 12--... support rod. 3rd Figure 6
Claims (1)
エーへの前記ペレット領域間に一メ′椿斜養す膚り形成
ル、前記ウェーハの周辺部に於仕る電界集中を抑制する
ための、周辺部の空所率を大きくした電極を用いて電気
泳動法にょ如前記メサ溝にガラス粉末を電着するように
し九ことを特徴とする半導体装置の製造方法。In order to suppress electric field concentration at the periphery of the wafer, a camellia slanting layer is formed between the pellet areas of the conductive conductor in which a large number of pellet regions are formed except for the periphery of the wafer. 9. A method of manufacturing a semiconductor device, characterized in that glass powder is electrodeposited in the mesa groove using an electrophoresis method using an electrode having a large void ratio in the peripheral portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56130557A JPS5832421A (en) | 1981-08-20 | 1981-08-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56130557A JPS5832421A (en) | 1981-08-20 | 1981-08-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5832421A true JPS5832421A (en) | 1983-02-25 |
Family
ID=15037108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56130557A Pending JPS5832421A (en) | 1981-08-20 | 1981-08-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5832421A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61263227A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS6331125A (en) * | 1986-07-25 | 1988-02-09 | Toshiba Components Kk | Manufacture of semiconductor device |
WO2016075787A1 (en) * | 2014-11-13 | 2016-05-19 | 新電元工業株式会社 | Method for manufacturing semiconductor device and glass coating forming device |
CN109121423A (en) * | 2017-04-19 | 2019-01-01 | 新电元工业株式会社 | The manufacturing method of semiconductor device |
-
1981
- 1981-08-20 JP JP56130557A patent/JPS5832421A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61263227A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPH0528492B2 (en) * | 1985-05-17 | 1993-04-26 | Matsushita Electronics Corp | |
JPS6331125A (en) * | 1986-07-25 | 1988-02-09 | Toshiba Components Kk | Manufacture of semiconductor device |
WO2016075787A1 (en) * | 2014-11-13 | 2016-05-19 | 新電元工業株式会社 | Method for manufacturing semiconductor device and glass coating forming device |
JP6029771B2 (en) * | 2014-11-13 | 2016-11-24 | 新電元工業株式会社 | Semiconductor device manufacturing method and glass film forming apparatus |
CN109121423A (en) * | 2017-04-19 | 2019-01-01 | 新电元工业株式会社 | The manufacturing method of semiconductor device |
TWI657512B (en) * | 2017-04-19 | 2019-04-21 | 新電元工業股份有限公司 | Method for manufacturing semiconductor device |
CN109121423B (en) * | 2017-04-19 | 2020-05-19 | 新电元工业株式会社 | Method for manufacturing semiconductor device |
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