JPS5829241A - Data communication system - Google Patents
Data communication systemInfo
- Publication number
- JPS5829241A JPS5829241A JP56127933A JP12793381A JPS5829241A JP S5829241 A JPS5829241 A JP S5829241A JP 56127933 A JP56127933 A JP 56127933A JP 12793381 A JP12793381 A JP 12793381A JP S5829241 A JPS5829241 A JP S5829241A
- Authority
- JP
- Japan
- Prior art keywords
- data
- receiver
- signal
- reception
- transmitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Bidirectional Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は牛二重通信システムによるデータ通信方式へ関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication system using a dual communication system.
(纂1図は従来のデータ通信方式による送受信器0)(
以下USARTという)ia分の回路図を示し、中央論
理演算i11!+(以下CPUという)から出力された
送信データを並直列変換し、ドライバ1B+ t−介し
て相手システムに信号を送出するとともに、相手システ
ムからの信号をレシーバ(4)を介して一人力し、これ
を直・並列変換してCPUI!IK入力するようにしで
ある・纂3図は亀1図回路によるデータ通信のタイムチ
ャートを示し、同図(イ)に示すように、l中ヤラクタ
分のデータがUSARTis)に入力されたと1、υ5
ART(13から同図−〇ようにRxRDYQi号が出
されることを示している0かくて上述のような従来例に
あっては、纂8図に示すように1中デラクタ分のデータ
が完全にUSART口1へ入力されないと、このυ!!
AI!Tl1)からRxRDY @号が一力されないえ
め、データの送受信の開始時に過値線を介した両側のシ
ステムで同時に送受信を行う可能性があり、通信障害を
起こす原因となる間慝があった。(The first diagram shows transmitter/receiver 0 using the conventional data communication method) (
The circuit diagram for ia (hereinafter referred to as USART) is shown, and the central logic operation i11! + (hereinafter referred to as CPU) converts the transmission data output from parallel to serial, sends a signal to the partner system via the driver 1B + t-, and receives the signal from the partner system via the receiver (4), Convert this to serial/parallel and use CPU! Figure 3 shows the time chart of data communication using the circuit shown in Figure 1, and as shown in Figure 1 (A), the data for Yarakuta in 1 is input to USARTis). υ5
ART (13 to 0 in the same figure indicates that the RxRDYQi number is issued. Therefore, in the conventional example described above, as shown in Fig. If it is not input to USART port 1, this υ!!
AI! Since the RxRDY @ signal was not activated from Tl1), there was a possibility that when data transmission and reception started, systems on both sides via the overvalue line were transmitting and receiving at the same time, leading to a communication failure.
本a明は上述の点に艦みて提供し次ものでありて、噛末
装置あるいはセンタ装置のUSARTにおけ!jl受信
データそのものをトリガ入力として、過信時には相手か
らの受信を、受信時には自システムからの送信を夫々不
可能とするととにより、送受信Oタイ−シラを明確にす
るようにし九データ過信方式を提供することを目的とす
るものでああ。The present invention is based on the above-mentioned points and provides the following, and it is provided in the USART of the end device or the center device! By using the received data itself as a trigger input and disabling reception from the other party during overconfidence, and disabling transmission from the own system during reception, a data overconfidence method is provided that clarifies the transmission and reception timing. Ah, what it is intended to do.
以下本発明の一実施例tWA面によシ詳述する0g1s
aiは本発明実施例の構成例を示し、図中111はCP
Uで伝送制御を行うものであシ、(1)はバーx−0り
て■え上記CPU(1)からの並列データを適轟な形の
直列データに変換して出力したり、あるいはまえ入って
11i良直列データを並列データに変換してCPUtt
lK肉は出力しえりするUSARTである・(s)は上
記υ5ARTIIIからの直列データを適幽なレベルに
変換するドライバ、(4)は受信データのレベル0ツブ
である。また纂4図は纂3図回路のタイムチャートを示
し、以下との纂4図タイムチャートにより#!$図実施
例の動作状1lt−示す0今信号線Lmに第4図中−に
示すような信号がきた場合、レシーバ(4)によってそ
の入力信号のレベルは同図(イ)のように変換されUS
ARTTl)に入力される0ま九このと魯レシーバ(4
)の出力は、リトリガプルリンショットフリップフ0ツ
ブ(暴)のT端子にトリ力信号として入力され、そのQ
出力は同図−のように立ち下り、ドライバ(3)はデイ
ゼープルされ、上記(偵の信号を受けとっている間、こ
のUSARTII)はデータを送信することができない
・ま九逆にこのUSART(rlが同図(力のような信
号を送信し、データを受信中でないならば、その信号は
ドライバiml Kよりて同図−のような信号に変換さ
れ、送信先に送ら′れる・このとき、ドライバts+の
出力からりトリカプルワシシヨットフリップフ0ツブ(
@)のT端子にトリガ入力が入シ、このリトリガプルヮ
ンシ1ットフリップフ0ツブ(@)のQ出力も同図(:
)のようになり、レシーバ14)がディセーブルされる
ので、このと自信号線Ll上にデータが乗りて禽てもそ
のデータはUSART(1)に入ることがない〇かくて
本発明にあっては、データの送受を行うKllし、先に
送信を開始したシステムのり−タの送受信が優先され、
データの送受信が同じタイニングで起るようなことがな
くなり、牛二重通信システムにおける送受信のタイ些ン
ジを明確化でき、これにより送受信のタイ三ンジの不良
に基く通信障害等を確Ij!に除去できる効果を有する
。Below, one embodiment of the present invention will be described in detail on the tWA plane.
ai indicates a configuration example of the embodiment of the present invention, and 111 in the figure is CP
Transmission control is performed by U, and (1) is used to convert the parallel data from the CPU (1) into serial data in an appropriate format and output it, or Enter 11i good serial data to parallel data and CPUtt
1K is the USART that outputs the output. (s) is the driver that converts the serial data from the υ5ARTIII to a suitable level, and (4) is the level 0 portion of the received data. Also, Figure 4 shows the time chart of the circuit shown in Figure 3, and according to the time chart of Figure 4 shown below, #! $Operation state of the embodiment 1lt-shows 0 If a signal as shown in FIG. 4 comes to the signal line Lm, the level of the input signal is converted by the receiver (4) as shown in the same figure (A) Been US
ARTTl) is input to the 0 and 9 receivers (4
) is input as a tri-force signal to the T terminal of the retrigger pull-in shot flip-flop, and its
The output falls as shown in the figure, the driver (3) is disabled, and the above (this USART II) cannot transmit data while receiving the reconnaissance signal. is transmitting a signal such as the one shown in the figure (Figure 1), and if no data is being received, the signal is converted by the driver iml K into a signal such as the one shown in the Figure - and sent to the destination. At this time, From the output of the driver ts+, the tri-coupled yacht flip-flop (
The trigger input is input to the T terminal of @), and the Q output of this retrigger pull-down switch (@) is also the same figure (:
), and the receiver 14) is disabled, so even if data gets on the self-signal line Ll, that data will not enter USART (1).Thus, according to the present invention, is the Kll that sends and receives data, and priority is given to the system router that started sending data first.
Data transmission and reception will no longer occur at the same tying, and the transmission and reception ties in the dual communication system can be clarified, thereby preventing communication failures caused by defects in the transmission and reception ties. It has the effect of removing
ところで上述のIN3図゛実施例のものにあっては、通
信の相手方であるシステムにソフトの暴走や回路の断線
乃至ショート等の障害が起った際、相手局からの過信を
八−ド的に受けつけないようにしているため、その異常
を膳識できない問題を有すゐ他、その^當の原因が自局
によるものか相手局による一〇かがiinで曹ない問題
がある◇そとでこのような障害の発生時にその障害の原
因を切り分けることがて禽るようにしたのが纂8発明で
あり、そp実施例を纂す図に示す0第5図において11
1〜(6)は前記第8図実施例と同様のものであ)、さ
もK(1)はリトリガプルヮシシヨットフリップフOツ
ブ、(81(slは夫々制御入力が−H”のとき閉じる
スイツチンク回路である・
躯6因はIII図実施例回路のタイムチャートを示し、
以下この第6図タイムチ?−)により纂す図回路の動作
状llt説明する。今第5図実施例回路において、II
e図(慣に示すようなり−タを送信中であるとすると、
リトリガプルヮシショットフリップフ0ツブ(・)のQ
は同図−のようになるから為スイッチンク回路(11)
は信号線Lst−開いて、前記II8図実施例と同様に
受信を受は付けないものであり、また同図(2)のよう
にデータを受信中は、リトリガプールワシシヨットフリ
ップフロップ監6)のQは同図(へ)のようになり、前
述と同様にデータの送信はで自ない・次に相手システム
が正常に動作していて、データの受信中に送信をおこな
っていなければ馬リトリガプルヮシシヨットフリップフ
0ツブ())のQは“H′″であるから、スイッチング
回路(1)は信号線Lvを閉じて、USARTislか
ら出力された送tIi信号は、ドライバ(3)、スイッ
チング回路1B)、レシーバ(4)を介してUSART
(1)にもどる。しかしながら相手システムが異常を起
していて受信中であるにもかかわらずデータを送信して
いる同図bすOような場合には、信号線LIKこの信号
が入る九め1リトリガプルワシシヨツトフリツプフOツ
ブ(マlOQ出力は同図口のように“Llとなp1スイ
ッチンタ回M T8)は信号線Lstl−開くので、U
SARTO)から出力されたデータ信号は前述のドライ
バ(3)、スイッチング回路18)ミレシーバ(4)の
回路を通ってUIART口)K戻ってζず、異常発生が
自己システムか相手システムかの切り分けができること
にな為・即ちこ0III図実施例のものにあっては、自
から出し九データがそのまま入力されているかどうかで
相手システムが正常に働いているか否かの判断かで論、
ま曳相手システムからACKないしはNAKの応答がな
いというような異常に対しても、1己システムの伝送制
御の誤りの有無が確認できるため、異常の原因をみつけ
ることが容易となるのである〇
本発明は上述のように構成したものであるから、複数の
システムから同時的にデータを送信しようとした場合に
おいて、先に送信を開始し九システムの9−夕が優先さ
れ、データの送受信が同じタイエンタで起らず送受信の
タイミンクが明確化できて通信障害を生じるようなこ“
とがない効果を有し、さらにms発明にあっては、上記
効果に加えて、幽から出したデータ信号がそのまま入力
されてiるかどうかで、通信障害が生じた場合のその原
因が自己システム側と相手システム側とのいずれの側に
生じているかを切り分けることがで自、異常発生時の対
応がより容易にで龜る効果を有するものである0By the way, in the above-mentioned IN3 diagram (embodiment), when a problem such as a runaway software or a circuit disconnection or short circuit occurs in the system at the other end of the communication, overconfidence from the other station is detected in an eight-way manner. In addition to the problem of not being able to recognize the abnormality, there is also the problem of not being able to determine whether the cause is caused by the own station or by the other station. Therefore, when such a failure occurs, it is possible to isolate the cause of the failure in the 8th invention, which is shown in Fig.
1 to (6) are the same as those in the embodiment shown in FIG. It is a switching circuit that closes when the circuit is closed.
Below is this figure 6 time chi? -) The operating state of the circuit will be explained below. Now, in the example circuit of FIG. 5, II
Figure e (assuming that the data is being sent as shown in
Q of retrigger pull shot flip flop (・)
The switching circuit (11) is as shown in the same figure.
The signal line Lst is open and reception is not accepted as in the embodiment shown in FIG. ) is as shown in the same figure (f), and data cannot be sent as described above.Next, if the other party's system is operating normally and the data is not being sent while receiving data, the data cannot be sent. Since the Q of the retrigger pull switch () is "H'", the switching circuit (1) closes the signal line Lv, and the transmission tIi signal output from the USARTisl is transmitted to the driver (3). ), switching circuit 1B), USART via receiver (4)
Return to (1). However, if the other system is malfunctioning and is transmitting data even though it is receiving data, the signal line LIK, which receives this signal, is connected to the ninth retrigger pull button. As shown in the figure, the output of the flip-flop Otub (M1OQ output becomes "Ll" as shown in the figure) and the signal line Lstl- is opened, so the U
The data signal output from SARTO passes through the aforementioned driver (3), switching circuit 18, and receiver (4) circuit and returns to the UIART port, making it easy to determine whether an error has occurred in the local system or the other system. In other words, in the case of the embodiment shown in Figure 0III, whether or not the other system is working normally depends on whether or not the original data is input as is.
Even if there is an abnormality such as no ACK or NAK response from the other system, it is possible to check whether there is an error in the transmission control of the own system, making it easier to find the cause of the abnormality. Since the invention is configured as described above, when attempting to transmit data from multiple systems simultaneously, transmission starts first and priority is given to the 9th system of the 9th system, so that data transmission and reception are the same. The timing of sending and receiving can be clarified without causing communication failures.
In addition to the above-mentioned effects, the ms invention also has the advantage that if a communication failure occurs, the cause of the problem is determined by whether or not the data signal emitted from the ghost is input as is. By distinguishing whether the problem is occurring on the system side or the partner system side, it has the effect of making it easier to respond when an abnormality occurs.
票1図は従来例の回路図、第8図は同上のタイムチャー
ト、118図は本発明の第1発明に係る実施例の回路図
、票4図は同上のタイムチャート、第5図は本発明の第
8発明に係る実施例の回路図、累・図は同上のタイムチ
ャートであり、(l)は送受信器(USART ’)で
ある0
代理人 弁理士 石 1)長 七Figure 1 is a circuit diagram of the conventional example, Figure 8 is a time chart of the same as above, Figure 118 is a circuit diagram of an embodiment according to the first invention of the present invention, Figure 4 is a time chart of the same as above, and Figure 5 is a time chart of the same as above. The circuit diagram and diagram of the embodiment according to the eighth invention are the same time charts as above, and (l) is the transmitter/receiver (USART').
Claims (1)
か−で、送受信器の送受信データそのものをトリn入力
として、送信時には相手からの受信を、受信時には自シ
ステムからの送信を夫々不可能にするように制御するこ
とt特徴とするり−タ過信方式〇 偉(亭二重通信システムによるデータ通信方式において
、送受信器の送受信データその4のをトリガ入力として
、送信時には相手からの受Iを、受信時には両局システ
ムからの過慣を夫々不可能くするように制御すると七−
K、送信時にその送信データが幽らO送受信器に戻って
くるか否かで相手システムの送受信タイニンクがとれて
いるか否かt判別し、通信異常時には1iiji6シス
テムが正常に動いているかどうかを判断して異常の原因
を叩)分けることができるようにしたことを特徴とする
一一夕通信方弐〇(1) Data communication method K using the zadou communication system
The data transmitted and received by the transmitter/receiver itself is input as input, and the data is controlled so that it is impossible to receive from the other party when transmitting, and to disable transmitting from the own system when receiving. Method 〇Wei (In the data communication method using the Tei dual communication system, the 4th transmission/reception data of the transmitter/receiver is used as a trigger input to make it impossible to receive reception from the other party when transmitting, and to prevent excessive reception from both systems when receiving. If controlled like this, 7-
K. At the time of transmission, whether or not the transmitted data returns to the O transmitter/receiver determines whether the transmission/reception timing of the other system is correct, and in the event of a communication error, it is determined whether the 1iiji6 system is operating normally. An instant communication method 2 that is characterized by being able to isolate the cause of an abnormality by
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56127933A JPS5829241A (en) | 1981-08-14 | 1981-08-14 | Data communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56127933A JPS5829241A (en) | 1981-08-14 | 1981-08-14 | Data communication system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5829241A true JPS5829241A (en) | 1983-02-21 |
Family
ID=14972219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56127933A Pending JPS5829241A (en) | 1981-08-14 | 1981-08-14 | Data communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5829241A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60169257A (en) * | 1983-12-14 | 1985-09-02 | ゼネラル・エレクトリック・カンパニイ | Digital data transceiver for power line communication system |
JPS6284244U (en) * | 1985-11-13 | 1987-05-29 |
-
1981
- 1981-08-14 JP JP56127933A patent/JPS5829241A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60169257A (en) * | 1983-12-14 | 1985-09-02 | ゼネラル・エレクトリック・カンパニイ | Digital data transceiver for power line communication system |
JPH0570348B2 (en) * | 1983-12-14 | 1993-10-04 | Gen Electric | |
JPS6284244U (en) * | 1985-11-13 | 1987-05-29 |
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