JPS5828830A - Formation of photo resist stencil - Google Patents
Formation of photo resist stencilInfo
- Publication number
- JPS5828830A JPS5828830A JP56117346A JP11734681A JPS5828830A JP S5828830 A JPS5828830 A JP S5828830A JP 56117346 A JP56117346 A JP 56117346A JP 11734681 A JP11734681 A JP 11734681A JP S5828830 A JPS5828830 A JP S5828830A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- exposed
- stencil
- photoresist
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
Abstract
Description
【発明の詳細な説明】
この発明はジ精セフソン集積回路等のリフトオフバター
ニングに利用されるフォトレジストステンシルの形成方
法に関慣るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming photoresist stencils used in lift-off patterning of semiconductor integrated circuits and the like.
リフトオフ法代は、第１図に示すような、断面構造が“
きのこ”型をしたフォトレジスト（第１図（ａ））ステ
ンシル（抜き型）の開孔部に、種々の薄膜層１２，１３
を推積し（第１図（ｂ））、ついでステンシルを構成す
るフォトレジスト層を有機浴媒を用いて溶融し去る際に
不要の薄膜層１３を除去して、所望のパターンを有する
薄膜層を得る（第１図（ｃ））方法である。ジョセフソ
ン集積回路の製造プロセスにおいては、薄膜層の開孔部
１４は接合領域に又薄膜層１２は超伝導線路に対比する
。The lift-off slope has a cross-sectional structure as shown in Figure 1.
Various thin film layers 12, 13 are placed in the opening of the mushroom-shaped photoresist (Fig. 1(a)) stencil (cutting die).
(FIG. 1(b)), and then, when the photoresist layer constituting the stencil is melted away using an organic bath medium, unnecessary thin film layer 13 is removed to form a thin film layer having a desired pattern. (Fig. 1(c)). In the Josephson integrated circuit manufacturing process, the apertures 14 in the thin film layer correspond to junction areas and the thin film layer 12 corresponds to superconducting lines.
第１図（ａ）はステンシルの形状パラメータＷ。Ｗ１Δ
を示すが、ステンシル基部の巾Ｗ１１は接合領域の形状
を規定し、罵は超伝導酬路の線巾を規定し、又４は薄膜
層１２．１３の５）離の難易度を決定する。FIG. 1(a) shows the shape parameter W of the stencil. W1Δ
However, the width W11 of the stencil base defines the shape of the bonding region, the width W11 defines the line width of the superconducting exchange path, and the width W11 determines the difficulty level of 5) separation of the thin film layers 12 and 13.
リフトオフ法、特にジ，セフソン集棺回闇のパターニン
グに用いられるリフトオフ法においては、ステンシルの
最大中Ｗ８．ひさしの深さΔ、基部の巾Ｗ、のいずれを
も制御よく、形成する必要かある。In the lift-off method, especially the lift-off method used for patterning the stencil's maximum medium W8. It is necessary to control both the depth Δ of the eaves and the width W of the base.
従来、このようなステンシルを得るためには、第一層と
なるポジ型フォトレジストを塗布・ペイキングし、第一
層表面を弗素を含む分子のガスプラズマ、例えば四フツ
化炭素ＣＦ、ガスプラガス中に曝し、第二層となるポジ
型フォトレジストを塗布・ペイキングして、二層構造フ
ォトレジスト層を形成する工程と、該二層構造フォトレ
ジスト層をマスク露光し、第二層を現憎し、第一層表面
を酸素プラズマ中に曝し、第一層を現像する工程よりな
るフォトレジストステンシルの形成方法が用いられた。Conventionally, in order to obtain such a stencil, a first layer of positive photoresist is coated and painted, and the surface of the first layer is immersed in a gas plasma of molecules containing fluorine, such as carbon tetrafluoride CF, gas plastic gas, etc. A step of exposing the two-layer structure photoresist layer to a second layer by applying and baking a positive photoresist layer to form a two-layer structure photoresist layer; A method of forming a photoresist stencil was used that consisted of exposing the surface of one layer to an oxygen plasma and developing the first layer.
この方法においては第一層の現像を行う際に、過現象に
よって発生するひさし構造によって”きのこ゛型断面を
有するステンシルを得ているのであり、びさし深さΔが
頭分でなかったり、基底部巾Ｗ、が制御しにくかったり
する欠点があった。In this method, when developing the first layer, a stencil with a mushroom-shaped cross section is obtained due to the eaves structure generated by an abnormal phenomenon, and the eaves depth Δ may not be the same as the head. There was a drawback that the base width W was difficult to control.
この本発明けこイシらの欠点を除去せしめたフォトレジ
ストステンシルの形成方法を提供することある。この発
明によれば第一層となるポジ型フォトレジストを塗布・
ペイキングし、第一層表面を弗素を含む分子のガスプラ
ズマに曝し、第二層となるポジ型フォトレジストを塗布
・ペイキングして、二層構造フォトレジスト層を形成す
る工程と、該二層構造レジスト層をマスク露光し、第二
層を現像し、第一層表面を酸素分子の含むカスのプラズ
マ中に曝し、第一層を現像する工程古、第一層のフすト
レジストと第二層のフォトレジストの未露光部分に対す
る溶解速度γ１．γ２の比γ、／ｒ２が１以上であるエ
ツチング液で、第二層をザイドエッチングする工程を含
む事を特徴とするフォトレジストステンシルの形成方法
が得られる。An object of the present invention is to provide a method for forming a photoresist stencil that eliminates the drawbacks of Kekoishi et al. According to this invention, the first layer of positive photoresist is applied and
baking, exposing the surface of the first layer to a gas plasma of molecules containing fluorine, and coating and baking a positive photoresist to form a second layer to form a two-layer photoresist layer; The resist layer is exposed to light using a mask, the second layer is developed, and the surface of the first layer is exposed to plasma containing scum containing oxygen molecules to develop the first layer. The dissolution rate γ1 for the unexposed portion of the photoresist. A method for forming a photoresist stencil is obtained, which includes the step of zide-etching the second layer with an etching solution having a ratio of γ2, /r2 of 1 or more.
前記この発明によれば形状パラメータの制御性のよいス
テンシル形成法を実現できる。According to the present invention, a stencil forming method with good controllability of shape parameters can be realized.
以下、この発明について図面を用いて詳細に説明する。Hereinafter, this invention will be explained in detail using the drawings.
第２図は、この発明の一実施例であるフォトレジストス
テンシルの形成プロセスを示す図面である。FIG. 2 is a diagram showing a process for forming a photoresist stencil according to an embodiment of the present invention.
基板２１上に第一層となるポジ型フォトレジスト２２を
塗布・ペイキングし、これを弗素を含む分子のプラズマ
（第１のプラズマ）中に曝すと、表面に耐診剤性の強化
された表面層２３が形成される。（第２図（ａ））。こ
の上に第二層となるポジ型フォトレジスト２４を塗布ペ
イキングする（第２図（ｂ））この二層構造フォトレジ
スト層をマスク露光し、第二層に対する現像液中に浸せ
ば、未感光配分を残して、第一層表面が露出する。この
時の未露光部分の巾をＷ、露光部分をＷとする。露出し
た第一層表面を酸素を含むプラズマ（第二のプラズマ）
中に曝して、耐溶剤性の強化された表面層２３をこの霧
出部分において除去し、第一層を現像すれば、第２図（
ｄ）の構造が得られる。When a positive photoresist 22 is coated and painted as a first layer on a substrate 21 and exposed to plasma of molecules containing fluorine (first plasma), a surface with enhanced resistance to diagnostic agents is formed on the surface. Layer 23 is formed. (Figure 2(a)). On top of this, a positive photoresist 24, which will become the second layer, is coated and baked (Fig. 2(b)). This two-layer structure photoresist layer is exposed to light using a mask and immersed in a developer for the second layer, leaving it unexposed. The first layer surface is exposed, leaving the distribution. The width of the unexposed portion at this time is W, and the width of the exposed portion is W. Oxygen-containing plasma (second plasma) is applied to the exposed first layer surface.
If the surface layer 23 with enhanced solvent resistance is removed at this sprayed portion and the first layer is developed, the resultant image shown in FIG.
The structure d) is obtained.
ついで、第一層のフォトレジストと第二層のフォトレジ
ストに対する溶解速度γ１．γ２の比γ、／γ２が１以
上であるエツチング液中に浸せば、第２図（ｅ）に示す
如く、きのこ型の断面を有するステンシルが得られる。Next, the dissolution rate γ1 for the first layer photoresist and the second layer photoresist is determined. By immersing the stencil in an etching solution in which the ratio γ, /γ2 is 1 or more, a stencil having a mushroom-shaped cross section as shown in FIG. 2(e) can be obtained.
ステンシルの形状パラメータＶＶ、、Ｗ８Δ、Ｗｏはマ
スクより転写された巾Ｗ。Ｗｌ、に対して次の関係にあ
る。Shape parameters VV, W8Δ, and Wo of the stencil are the width W transferred from the mask. The following relationship exists for Wl.
嶌、＝Ｗ、、＋２７．−を 鴨＝〜Ｉ宿−２γＩＩｌｌ ■ｉ−呵、−２γ２・ｔ Δ−（７’２−１１）・ｔ ここにｔ′はサイドエッチングの時間である。Shima, =W,, +27. - Duck=~I-2γIIll ■i−呵、−2γ2・t Δ-(7'2-11)・t Here, t' is the side etching time.
第一、第二のフォトレジストの種類及び膜厚、第一、第
二のプラズマの種々、サイドエツチングのためのエツチ
ング液等は、得るべきフォトレジストステンシルの使用
目的に応じて、形状パラメータの大きさ及び鞘層、プロ
セスにおける耐件等につき、所期の性能を満たすように
、選択する必要がある。−例として、第一、第二のフォ
トレジストとして商品名ＡＺ１３７０、ＡＺ２４１５、
第一のプラズマとしで純四フッ化炭素ガスプラズマ、第
二のプラズマとして純酸素プラズマ、サイドエツチング
のためのエツチング液として商品名ＡＺ２４０１を適当
な量の水で稀釈したものを用いる事ができる。The type and film thickness of the first and second photoresists, the variety of first and second plasmas, the etching liquid for side etching, etc. are determined depending on the size of the shape parameters depending on the purpose of use of the photoresist stencil to be obtained. It is necessary to select the sheath layer, sheath layer, process resistance, etc. to meet the desired performance. - For example, as the first and second photoresists, product names AZ1370, AZ2415,
Pure carbon tetrafluoride gas plasma can be used as the first plasma, pure oxygen plasma can be used as the second plasma, and AZ2401 (trade name) diluted with an appropriate amount of water can be used as the etching liquid for side etching.
以上述べたようにこの発明による、フォトレジストステ
ンシル形成法においては、ステンシルの重要なパラメー
タの大きさ及び確度は、フォトマスノ上のパターンの大
きさ及び精度と、サイドエッチングの時間及び制御精度
のみによって決定されるので、極めて、制御よく、所期
のきのこ型断面を有するステンシルか（４）られ、リフ
トオフ法による回路パターニングに利用して、その益す
るところ犬である。As described above, in the photoresist stencil forming method according to the present invention, the size and accuracy of the important parameters of the stencil are determined only by the size and accuracy of the pattern on the photomass plate, and the time and control accuracy of side etching. As a result, a stencil with a desired mushroom-shaped cross-section can be produced in a very controlled manner (4), and can be used for circuit patterning by the lift-off method to its advantage.
第１図（ａ）、（ｂ）、（ｃ）はフォトレジストステン
シルの形状パラメータ及びリットオフ法によるパターニ
ングを説明するための図面である。図において、１１は
フォトレジスト１２，１３は薄膜層、１４は開口部を示
す。
第２図（ａ）〜（ｅ）はこの発明の一実施例であるフォ
トレジストステンンルの形成プロセスを説明するだめの
図面である。
図において２１は基板、２２．２４はポジ型フォトレジ
スト、２３は表面層を示す。FIGS. 1(a), (b), and (c) are drawings for explaining shape parameters of a photoresist stencil and patterning by the lit-off method. In the figure, reference numeral 11 indicates photoresists 12 and 13 thin film layers, and reference numeral 14 indicates an opening. FIGS. 2(a) to 2(e) are diagrams illustrating a process for forming a photoresist trench according to an embodiment of the present invention. In the figure, 21 is a substrate, 22, 24 is a positive photoresist, and 23 is a surface layer.
Claims (1)
し、第一層表面を弗素を含む分子のガスプラスマに曝し
、第二層となるポジ型フォトレジストを塗布・ベイキン
グして、二層構造フォトレジスト層を形成する工程と、
該二層構造フォトレジスト層をマスク露光し、第二層を
現像し、第一層表面を酸素分子を含むガスのプラズマ中
に曝し、第一層を現像する工程と、第一層フォトレジス
トと第二層のフォトレジストの未露光部分に対する溶解
速度ｒ、、ｒ、の比ｒ、／ｒ２が１以上であるエッチン
ク液で第二層をサイドエッチングする工程を含む事を特
徴とするフォトレジストステンシルの形成方法。The first layer of positive photoresist is coated and baked, the surface of the first layer is exposed to a gas plasma of molecules containing fluorine, and the second layer of positive photoresist is coated and baked to form a two-layer photoresist. a step of forming a layer;
A step of exposing the two-layer structure photoresist layer to light using a mask, developing the second layer, exposing the surface of the first layer to plasma of a gas containing oxygen molecules, and developing the first layer; A photoresist stencil characterized by including a step of side etching the second layer with an etching liquid having a ratio r, /r2 of dissolution rate r, , r, to the unexposed portion of the second layer photoresist. How to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56117346A JPS5828830A (en) | 1981-07-27 | 1981-07-27 | Formation of photo resist stencil |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56117346A JPS5828830A (en) | 1981-07-27 | 1981-07-27 | Formation of photo resist stencil |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5828830A true JPS5828830A (en) | 1983-02-19 |
| JPH0239090B2 JPH0239090B2 (en) | 1990-09-04 |
Family
ID=14709418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56117346A Granted JPS5828830A (en) | 1981-07-27 | 1981-07-27 | Formation of photo resist stencil |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5828830A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5255175A (en) * | 1989-05-15 | 1993-10-19 | Kabushiki Kaisha Toshiba | Power generation system having induction generator and controlled bridge rectifier |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55154737A (en) * | 1979-05-22 | 1980-12-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of forming pattern |
| JPS5655055A (en) * | 1979-10-12 | 1981-05-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5691434A (en) * | 1979-12-26 | 1981-07-24 | Fujitsu Ltd | Method for forming pattern of deposited film by lift-off method |
-
1981
- 1981-07-27 JP JP56117346A patent/JPS5828830A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55154737A (en) * | 1979-05-22 | 1980-12-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of forming pattern |
| JPS5655055A (en) * | 1979-10-12 | 1981-05-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5691434A (en) * | 1979-12-26 | 1981-07-24 | Fujitsu Ltd | Method for forming pattern of deposited film by lift-off method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5255175A (en) * | 1989-05-15 | 1993-10-19 | Kabushiki Kaisha Toshiba | Power generation system having induction generator and controlled bridge rectifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0239090B2 (en) | 1990-09-04 |
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