JPS5827350A - Mounting method for ic - Google Patents
Mounting method for icInfo
- Publication number
- JPS5827350A JPS5827350A JP56125477A JP12547781A JPS5827350A JP S5827350 A JPS5827350 A JP S5827350A JP 56125477 A JP56125477 A JP 56125477A JP 12547781 A JP12547781 A JP 12547781A JP S5827350 A JPS5827350 A JP S5827350A
- Authority
- JP
- Japan
- Prior art keywords
- backing plate
- circuit board
- carrier
- resin
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子の薄型実装方法の改良に関するもの
である。腕時計モジュール等の小型装置に於て、装置の
一層の小型化、薄型化を図るために、半導体素子の実装
構造のより小型化、薄型化の要求は益々高まっている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a thin mounting method for semiconductor devices. In order to further reduce the size and thickness of small devices such as wristwatch modules, there is an increasing demand for smaller and thinner mounting structures for semiconductor elements.
耐熱性樹脂基板上に銅箔を貼って、フォトエツチング法
により回路ノ;ターンを形成した回路基板に、半導体素
子を固定した後、Au線又はAl線によって前記半導体
素子上の外部接続電極と、前記回路基板上の対応するパ
ターンとを接続する所謂ワイヤボンディング法に於て、
薄型化を達成する方法として、回路基板に半導体素子を
搭載するために予めプレスその他により貫通孔を穿設し
、回路パターンと反対側に別な薄板材より成る裏打板を
固着させておいて、該裏打板上に前記半導体素子を固定
する方法が実用化されている〇
この方法を採用することにより、半導体を回路基板に設
けられた凹部に落し込んだ状態で固定することができる
ので、ワイヤボンディング法による実装構造を前記凹部
の深さ分だけ薄(し、又これに伴って平面方向に於ける
ワイヤーの張り出し量が少くてすむので、その分だけ半
導体素子の実装面積を小さくすることができる。After fixing a semiconductor element to a circuit board on which a copper foil is pasted on a heat-resistant resin substrate and circuit turns are formed by photoetching, an external connection electrode on the semiconductor element is connected to the circuit board using an Au wire or an Al wire. In the so-called wire bonding method for connecting the corresponding patterns on the circuit board,
As a method of achieving thinness, a through hole is previously formed by pressing or other means in order to mount a semiconductor element on a circuit board, and a backing plate made of a different thin plate material is fixed to the side opposite to the circuit pattern. A method of fixing the semiconductor element on the backing plate has been put into practical use. By adopting this method, the semiconductor can be fixed while being dropped into the recess provided in the circuit board, so the wires can be fixed. The mounting structure formed by the bonding method is made thinner by the depth of the recess (and as a result, the amount of wire protruding in the plane direction can be reduced, so the mounting area of the semiconductor element can be reduced by that amount). can.
しかるに、上記の従来の方法の欠点は、回路基板を製作
するための特別な機械設備を必要とし、又は回路基板を
農作するための工数が少ながらず増大することであった
。すなわち前記裏打板を固着させるために、熱圧着機な
どの高価な機械設備を必要とし、さらに接着のための工
数を要し、加工工数の増大を伴う等の欠点を有していた
。However, the drawbacks of the above-mentioned conventional methods are that special machinery and equipment are required to manufacture the circuit boards, or the number of man-hours required to produce the circuit boards increases. That is, in order to fix the backing plate, expensive mechanical equipment such as a thermocompression bonding machine is required, and the number of steps required for adhesion is also increased, resulting in an increase in the number of processing steps.
本発明の目的は、上記欠点を解決し設備費や工数の増大
をもたらす事なく初期の目的であるICの小型化、薄型
化を実現する実装方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a mounting method that solves the above drawbacks and achieves the initial objective of making an IC smaller and thinner without increasing equipment costs and man-hours.
上記目的を達成するための本発明の要旨は、実装工程に
使用するキャリアーに、裏打板を収納し位置決めするた
めの凹部を設ける事により、封止樹脂が硬化する際に併
せて回路基板と裏打板とを接着させることによって、回
路基板と裏打板とを予め接着させておくという工程を省
(ことにある。The gist of the present invention to achieve the above object is to provide a recess for storing and positioning the backing plate in the carrier used in the mounting process, so that when the sealing resin hardens, the circuit board and the backing plate are By adhering the circuit board and the backing board, the process of adhering the circuit board and the backing board in advance can be eliminated.
以下図によって本発明の実施例を加工工程順に詳述する
。Embodiments of the present invention will be described in detail below in the order of processing steps with reference to the drawings.
第1図は本発明に於る各工程に共通して使用するキャリ
アーに於るIC実装部の断面図を示す。FIG. 1 shows a sectional view of an IC mounting part in a carrier commonly used in each process of the present invention.
1はキャリアーであり、鋼材、アルミニウム材、耐熱性
樹脂材などを加工して形成され、後述する裏打板をわず
がな隙間を以って収納し得るように穿設された凹部1a
と、後述する回路基板を位置決めするための複数のビン
1bを有している。尚該キャリアー1は回路基板単個用
であっても複数個連続載置用であっても良い。Reference numeral 1 denotes a carrier, which is formed by processing steel material, aluminum material, heat-resistant resin material, etc., and has a recess 1a formed so as to accommodate a backing plate, which will be described later, with a slight gap.
and a plurality of bins 1b for positioning circuit boards to be described later. Note that the carrier 1 may be for a single circuit board or for continuously mounting a plurality of circuit boards.
第2図(a)〜(e)は本発明によるIC実装部を工程
順に示した断面図である。FIGS. 2(a) to 2(e) are cross-sectional views showing the IC mounting part according to the present invention in the order of steps.
第2図(a)は、キャリアー1に裏打板2と回路基板3
とが搭載された状態でのIC実装部の断面図である。前
記裏打板2は金属又は、樹脂で形成されたシートで、キ
ャリアー1の凹部1aにわずかの隙間をもって収納され
る。Figure 2 (a) shows a carrier 1, a backing plate 2 and a circuit board 3.
FIG. 3 is a cross-sectional view of the IC mounting section in a state where the IC mounting part is mounted. The backing plate 2 is a sheet made of metal or resin, and is housed in the recess 1a of the carrier 1 with a slight gap.
3は回路基板であり、上面に回路パターン6cが配設さ
れ、ICを埋設するための貫通したデバイス孔6bが穿
設されており、複数の位置決め孔6aが設げられ、該位
置決め孔3aと前記キャリアー1のピン1bとが嵌合し
て、前記キャリアー1の上に搭載される。3 is a circuit board, which has a circuit pattern 6c on its upper surface, a penetrating device hole 6b for embedding an IC, and a plurality of positioning holes 6a. The pin 1b of the carrier 1 fits into the carrier 1, and the carrier 1 is mounted on the carrier 1.
第2図(b)は、IC・4を接着した状態のIC実装部
の断面図である。前記回路基板6のデバイス孔6bの中
でかつ前記裏打板20表面に、熱硬化性樹脂接着剤5を
滴下し、さらにIC4を搭載して接着する。FIG. 2(b) is a sectional view of the IC mounting part with the IC 4 bonded thereto. A thermosetting resin adhesive 5 is dropped into the device hole 6b of the circuit board 6 and on the surface of the backing plate 20, and then the IC 4 is mounted and bonded.
第2図(e)は1次の工程でワイヤボンディングされた
状態のIC実装部の断面図である。IC40表面に設け
られた接続電極と、回路基板6上に設けられた回路パタ
ーン6CとをAu線又はAl線より成るボンディングワ
イヤー6にて接続する。FIG. 2(e) is a sectional view of the IC mounting part in a state where wire bonding has been performed in the first step. The connection electrode provided on the surface of the IC 40 and the circuit pattern 6C provided on the circuit board 6 are connected by a bonding wire 6 made of an Au wire or an Al wire.
第2図(d)は、IC4の周囲を封止樹脂7で封止した
状態のIC実装部の断面図である。エポキシ樹脂等で成
る封止樹脂7を吐出装置を用いて、前記ICJ上及び周
辺に適量供給し、さらてキャリアー1ごとキュアー炉に
通して前記封止樹脂7を硬化させる。FIG. 2(d) is a sectional view of the IC mounting part in a state where the periphery of the IC 4 is sealed with the sealing resin 7. An appropriate amount of sealing resin 7 made of epoxy resin or the like is supplied onto and around the ICJ using a dispensing device, and the carrier 1 is then passed through a curing furnace to harden the sealing resin 7.
封止樹脂7の供給量は、少くとも回路基板乙のデバイス
孔6bとIC4との間隙8を埋め尽して、さらにIC4
と前記ボンディングワイヤー6とを完全に覆うように調
整しておく。The supply amount of the sealing resin 7 is such that it fills at least the gap 8 between the device hole 6b of the circuit board B and the IC4, and further fills the gap 8 between the IC4 and the device hole 6b of the circuit board B.
and the bonding wire 6 are adjusted so as to completely cover them.
この際、前記封止樹脂7は前記間隙8に充填され、間隙
8の底部の裏打板2に達し、さらに前記回路基板6と裏
打板2との間のわずかなすきま9にも流れ込むため、前
記封止樹脂7が硬化する際、同時に前記裏打板2と前記
回路基板3とを接着固定させることが出来る。At this time, the sealing resin 7 fills the gap 8, reaches the backing plate 2 at the bottom of the gap 8, and also flows into the slight gap 9 between the circuit board 6 and the backing plate 2, so that When the sealing resin 7 hardens, the backing plate 2 and the circuit board 3 can be adhesively fixed at the same time.
第2図(e)は、封止樹脂7が硬化した後に、回路基板
3を前記キャリアー1から取外した状態のIC実装部の
断面図である。裏打板2は既に回路基板3に接着されて
おり、これがICの実装を完了した状態である。FIG. 2(e) is a sectional view of the IC mounting portion with the circuit board 3 removed from the carrier 1 after the sealing resin 7 has hardened. The backing plate 2 has already been bonded to the circuit board 3, and this is the state in which the IC mounting is completed.
第3図、第4図、第5図、第6図はそれぞれ本発明の別
な実施例を示すIC実装部の断面図である。FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are sectional views of an IC mounting portion showing other embodiments of the present invention.
前述の第2図(d)の説明に於て、裏打板2と回路基板
3との接着力をより高めるために、第3図の如く回路基
板乙の裏面に予め機械加工で浅い浚い6dを設け、或は
第4図の如く裏打板2の成形・の際に浅い凹み2aを片
面又は両面に設げておいて、前記裏打板2と前記回路基
板3との間に、前記封止樹脂7が流れ込み易くしても良
いし、更に第5図の如く、裏打板2に貫通孔2bを設け
て封止樹脂7によるアンカー効果をもたらすこともでき
る。又第5図に示す如く封止樹脂流れ防止用の枠10を
使用する技術は公知であり前述のどの実施例と組合せて
使用しても差支えない。In the explanation of FIG. 2(d) above, in order to further increase the adhesion between the backing plate 2 and the circuit board 3, a shallow dredge 6d was pre-machined on the back surface of the circuit board B as shown in FIG. Alternatively, as shown in FIG. The sealing resin 7 may easily flow into the sealing resin 7, or the backing plate 2 may be provided with through holes 2b as shown in FIG. Further, as shown in FIG. 5, the technique of using a frame 10 for preventing the sealing resin from flowing is well known and may be used in combination with any of the embodiments described above.
又前述の第2図(b)及び(C)で説明した工程に於て
、裏打板2がキャリアーの凹み1aの中でわずかに動く
のを防ぐために、第6図に示す如くキャリアー1に貫通
穴1Cを穿設して、該貫通穴1c内を真空で引くことに
より、前記裏打板2を前記キャリアー1に吸着固定して
もよい。In addition, in the steps explained in FIGS. 2(b) and 2(C) above, in order to prevent the backing plate 2 from moving slightly in the recess 1a of the carrier, a hole is inserted through the carrier 1 as shown in FIG. The backing plate 2 may be fixed to the carrier 1 by suction by drilling a hole 1C and drawing a vacuum inside the through hole 1c.
以上の如き一連の工程を経て構成された半導体素子の実
装構造は、信頼性試験に於て従来の半導体素子を落し込
んだ実装構造と比較して同等の性能が得られた。The semiconductor element mounting structure constructed through the series of steps described above achieved performance equivalent to that of a conventional mounting structure in which a semiconductor element was mounted in a reliability test.
以上に述べたごとく、キャリアーに裏打板を収納する凹
部を設けた事により、樹脂封止する隙に封止用樹脂で樹
脂封止すると共に回路基板と裏杓板との接着が可能とな
るため、回路基板に裏打板を予め接着しておく工程が不
要となり、回路基板の製造上特別な設備を必要とせず、
又回路基板の製造工程を含めた実装工程全体として、従
来の方法に比して加工工数の短縮ができ、薄型、小型で
かつ廉価なICの実装方法を実現することができた。As mentioned above, by providing the recessed part in the carrier to accommodate the backing plate, it is possible to resin-seal with sealing resin in the gap for resin sealing and to bond the circuit board and the backing plate. , there is no need for the process of adhering the backing plate to the circuit board in advance, and no special equipment is required for manufacturing the circuit board.
In addition, in the entire mounting process including the manufacturing process of the circuit board, the number of processing steps can be reduced compared to conventional methods, and a thinner, smaller, and less expensive IC mounting method can be realized.
第1図は本発明に用いたキャリアーの部分断面図。第2
図(a)〜(e)は本発明に於るIC実装工程を示すI
C実装部の断面図。第3図、第4図、第5図、第6図は
それぞれ本発明の別な実施例を示す部分断面図。
1・・・・・・キャリアー、2・・・・・・裏打板、6
・・・・・・回路基板、 4・・・・・・ICl3・・
・・・樹脂接着剤、7・・・・・・封止樹脂。
第1図
第2図
(Q)
(b)
ム
第2図
(d)
(e)FIG. 1 is a partial sectional view of a carrier used in the present invention. Second
Figures (a) to (e) show the IC mounting process in the present invention.
C sectional view of the mounting part. FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are partial sectional views showing other embodiments of the present invention. 1...Carrier, 2...Backing board, 6
......Circuit board, 4...ICl3...
... Resin adhesive, 7... Sealing resin. Figure 1 Figure 2 (Q) (b) Figure 2 (d) (e)
Claims (1)
、該裏打板にICを接着するとともに、ワイヤーボ/デ
ィ/グ、樹脂封止する実装方法に於て、前記実装工程に
使用するキャリアーに、前記裏打板を収納するための凹
部を設け、前記キャリアーにより回路基板のデバイス孔
と裏打板とを位置決め接触させた状態で樹脂封止を行う
ことにより、封止樹脂が硬化する際に併せて前記回路基
板と裏打板とを接着固定させることを特徴とするICの
実装方法。In a mounting method in which a backing plate is fixed to the back side of a device hole provided in a circuit board, an IC is bonded to the backing plate, and the wire board/diag/g is sealed with resin, the carrier used in the mounting process is A recessed portion is provided to accommodate the backing plate, and resin sealing is performed with the device hole of the circuit board and the backing plate positioned and in contact with the carrier, so that when the sealing resin hardens, A method for mounting an IC, characterized in that the circuit board and the backing plate are fixed by adhesive.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56125477A JPS5827350A (en) | 1981-08-11 | 1981-08-11 | Mounting method for ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56125477A JPS5827350A (en) | 1981-08-11 | 1981-08-11 | Mounting method for ic |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5827350A true JPS5827350A (en) | 1983-02-18 |
JPS6351376B2 JPS6351376B2 (en) | 1988-10-13 |
Family
ID=14911052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56125477A Granted JPS5827350A (en) | 1981-08-11 | 1981-08-11 | Mounting method for ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5827350A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2805392A1 (en) * | 2000-02-17 | 2001-08-24 | Bull Sa | OVER-INTEGRATED CIRCUIT BOX |
-
1981
- 1981-08-11 JP JP56125477A patent/JPS5827350A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2805392A1 (en) * | 2000-02-17 | 2001-08-24 | Bull Sa | OVER-INTEGRATED CIRCUIT BOX |
EP1130641A1 (en) * | 2000-02-17 | 2001-09-05 | Bull S.A. | Molded integrated circuit package |
Also Published As
Publication number | Publication date |
---|---|
JPS6351376B2 (en) | 1988-10-13 |
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