JPH10173085A - Electronic module and manufacturing method of electronic module - Google Patents
Electronic module and manufacturing method of electronic moduleInfo
- Publication number
- JPH10173085A JPH10173085A JP8326522A JP32652296A JPH10173085A JP H10173085 A JPH10173085 A JP H10173085A JP 8326522 A JP8326522 A JP 8326522A JP 32652296 A JP32652296 A JP 32652296A JP H10173085 A JPH10173085 A JP H10173085A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- electronic module
- wiring board
- printed wiring
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は印刷配線板にベアチ
ップを実装して成る電子モジュール及びその製造方法に
関する。[0001] 1. Field of the Invention [0002] The present invention relates to an electronic module comprising a printed circuit board and a bare chip mounted thereon, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】ＰＣカードモジュールなどの電子機器組
み立てにおける従来のベアチップ実装方法、特にワイヤ
ボンディングによる方法は、図５に示した実装プロセス
によりなされる。即ち、図４に示した電子モジュールの
印刷配線板５のダイパッド４にダイペーストを転写（ス
テップ５０１）する。次にベアチップＩＣ１などの電子
部品をこのダイペースト上に装着（ステップ５０２のダ
イボンディング）し、このダイペーストを熱硬化（ステ
ップ５０３）して固定する。次にベアチップＩＣと回路
パターン６間を接続する金ワイヤー２などのワイヤボン
ディング（ステップ５０４）を実施した後、樹脂７の封
止（ステップ５０５）及び熱硬化（ステップ５０６）を
行って、実装完了となる。その後、ステップ５０７にて
ベアチップＩＣ１の動作試験を行って、実装プロセスを
終了する。2. Description of the Related Art A conventional bare chip mounting method for assembling electronic equipment such as a PC card module, particularly a method using wire bonding, is performed by a mounting process shown in FIG. That is, the die paste is transferred to the die pad 4 of the printed wiring board 5 of the electronic module shown in FIG. 4 (Step 501). Next, an electronic component such as a bare chip IC1 is mounted on the die paste (die bonding in step 502), and the die paste is thermally cured (step 503) and fixed. Next, after performing wire bonding (step 504) of the gold wire 2 or the like for connecting the bare chip IC and the circuit pattern 6, sealing of the resin 7 (step 505) and thermosetting (step 506) are performed to complete the mounting. Becomes Thereafter, in step 507, an operation test of the bare chip IC1 is performed, and the mounting process ends.
【０００３】このような従来のベアチップＩＣ１の実装
方法は最も完成された方法であるが、ＰＣカードモジュ
ールのような製品仕様の基本である外形寸法の厚みに制
約を設けた場合、図４に示した（ｔ＋Ｔ）がこの制約を
受ける。このため、樹脂７による封止の際に、この樹脂
の厚みが少しでも厚くなると、前記厚み規制をクリアー
できなくなるため、樹脂７の封止作業を難しくして、作
業効率が下がってしまうという不具合があると共に、顕
微鏡検査及び高さ測定及びリペアーなどの工数増加によ
る作業負荷を増大させる原因となっている。[0003] Such a conventional method of mounting the bare chip IC 1 is the most completed method. However, when the thickness of the external dimensions, which is the basis of product specifications such as a PC card module, is limited, the method shown in FIG. (T + T) is subject to this constraint. For this reason, when the thickness of the resin is slightly increased during sealing with the resin 7, the thickness regulation cannot be satisfied, and the sealing operation of the resin 7 becomes difficult, resulting in a decrease in work efficiency. In addition to this, the work load increases due to an increase in man-hours such as microscopic inspection, height measurement, and repair.
【０００４】[0004]
【発明が解決しようとする課題】上記のように、ＰＣカ
ードモジュールのようなカード製品の場合、カードの外
形寸法制約、特に厚み規制は樹脂７の封止時の厚みを規
制するため、ベアチップ実装時の制約となり、上記した
樹脂７の封止作業を困難にし、作業効率を低下させてし
まうという課題があると共に、顕微鏡検査及び高さ測定
及びリペアーなど、組立工数を増大させてしまうという
課題があった。As described above, in the case of a card product such as a PC card module, the outer dimensions of the card, especially the thickness regulation, regulates the thickness when the resin 7 is sealed. However, there is a problem that the sealing work of the resin 7 described above becomes difficult and the work efficiency is reduced, and a problem that the number of assembling steps such as microscopic inspection, height measurement and repair is increased. there were.
【０００５】そこで本発明は上記のような課題を解決す
るためになされたもので、厚み規制がある電子モジュー
ルにおいてもベアチップＩＣの実装を容易として、前記
電子モジュールの製造効率を向上さることができる電子
モジュール及びその製造方法を提供することを目的とし
ている。Accordingly, the present invention has been made to solve the above-described problems, and it is possible to easily mount a bare chip IC even in an electronic module having a restricted thickness, thereby improving the manufacturing efficiency of the electronic module. An object is to provide an electronic module and a method for manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】請求項１の発明は、表面
にパターンを形成した印刷配線板と、この印刷配線板に
穿かれた凹部と、この凹部に収容されて前記印刷配線板
に実装されたベアチップとを具備する構成を備えてい
る。According to a first aspect of the present invention, there is provided a printed wiring board having a pattern formed on a surface thereof, a recess formed in the printed wiring board, and a recess accommodated in the recess and mounted on the printed wiring board. And a bare chip provided.
【０００７】このような構成により、ベアチップを実装
して成る電子モジュールの厚みが、前記凹部の深さだけ
薄くなる。[0007] With this configuration, the thickness of the electronic module on which the bare chip is mounted is reduced by the depth of the recess.
【０００８】請求項２の発明は、前記凹部に収容された
ベアチップを上部から封止する樹脂を有する構成を備え
ている。According to a second aspect of the present invention, there is provided a structure having a resin for sealing the bare chip housed in the concave portion from above.
【０００９】このような構成により、ベアチップを上部
から封止する樹脂を含めた電子モジュールの厚みが、前
記凹部の深さだけ薄くなる。With such a configuration, the thickness of the electronic module including the resin for sealing the bare chip from above is reduced by the depth of the recess.
【００１０】請求項３の発明は、表面にパターンを形成
した印刷配線板にベアチップを実装して製造される電子
モジュールの製造方法において、前記印刷配線板に凹部
を穿ち、この凹部に前記ベアチップを収容し、この収容
したベアチップを前記凹部に接着剤で接着して固定した
後ワイヤボンディングを施し、更にこのベアチップの上
部から樹脂封止を施す構成を備えている。According to a third aspect of the present invention, there is provided a method of manufacturing an electronic module in which a bare chip is mounted on a printed wiring board having a pattern formed on a surface thereof, wherein a recess is formed in the printed wiring board, and the bare chip is inserted into the recess. The bare chip is housed in the recess, and the bare chip is bonded and fixed to the recess with an adhesive, wire bonding is performed, and resin sealing is performed from above the bare chip.
【００１１】このような構成により、ベアチップを上部
から封止する樹脂を含めた電子モジュールの厚みが、前
記凹部の深さだけ薄くなる。With such a configuration, the thickness of the electronic module including the resin for sealing the bare chip from above is reduced by the depth of the recess.
【００１２】請求項４の発明の前記凹部は、前記印刷配
線板に穿かれた開口孔と、この開口孔を裏側から塞ぐよ
うに前記印刷配線板の裏側から張り付けられた耐熱性フ
ィルムとにより構成され、このような凹部に前記ベアチ
ップを実装した後、前記耐熱性フィルムを剥離する構成
を備えている。According to a fourth aspect of the present invention, the concave portion includes an opening formed in the printed wiring board, and a heat-resistant film adhered from the back side of the printed wiring board so as to cover the opening from the back. After the bare chip is mounted in such a recess, the heat-resistant film is peeled off.
【００１３】このような構成により、凹部の深さが最大
となって、ベアチップを上部から封止する樹脂を含めた
電子モジュールの厚みが、更に薄くなる。With this configuration, the depth of the concave portion is maximized, and the thickness of the electronic module including the resin for sealing the bare chip from above is further reduced.
【００１４】請求項５の発明の前記電子モジュールはＰ
Ｃカードモジュールである構成を備えている。According to a fifth aspect of the present invention, the electronic module is a P module.
It has a configuration that is a C card module.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。図１は本発明の電子モジュールの
一実施の形態の構成を示したブロック図である。１は印
刷配線板５の開口孔に実装されたベアチップＩＣ、２は
ベアチップＩＣ１と印刷配線板５上のパターン（回路パ
ターン）６を電気的に接続する金ワイヤー、３はベアチ
ップＩＣ１の側面を印刷配線板５に接着して固定する導
電性の接着剤、５はフェノール樹脂などからなる印刷配
線板、６は印刷配線板５上に形成される回路パターン、
７はベアチップＩＣ１部分を上部から封止する樹脂、８
はベアチップＩＣ１の実装時に印刷配線板５の開口孔を
裏側から塞ぐように印刷配線板５の裏面に張り付けられ
る耐熱性フィルムである。尚、ベアチップＩＣ１の実装
完了後、耐熱性フィルム８は剥離され、この状態で電子
モジュールの組み立てが完成する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the electronic module of the present invention. 1 is a bare chip IC mounted in an opening of the printed wiring board 5, 2 is a gold wire for electrically connecting the bare chip IC 1 and a pattern (circuit pattern) 6 on the printed wiring board 5, and 3 is a side surface of the bare chip IC 1. A conductive adhesive that is adhered and fixed to the wiring board 5; 5 is a printed wiring board made of phenol resin or the like; 6 is a circuit pattern formed on the printed wiring board 5;
7 is a resin for sealing the bare chip IC1 from above, 8
Is a heat-resistant film attached to the back surface of the printed wiring board 5 so as to cover the opening of the printed wiring board 5 from the back side when the bare chip IC 1 is mounted. After the mounting of the bare chip IC1, the heat-resistant film 8 is peeled off, and the assembly of the electronic module is completed in this state.
【００１６】次に上記した電子モジュールの製造方法に
ついて図３のフローを参照して説明する。まず、図１に
示した電子モジュールにベアチップＩＣ１を実装する前
の状態は、図２に示す如くであり、印刷配線板５に穿か
れた開口孔Ａの裏面が塞がるように耐熱性フィルム８を
印刷配線板５の裏面に張る。こうしておいてからベアチ
ップＩＣ１を開口孔Ａ内の耐熱性フィルム８上にダイマ
ウント（ステップ３０１）する。次にベアチップＩＣ１
の側面と開口孔Ａの内側面の間にディスペンサーでダイ
ペーストなどの接着剤を充填（ステップ３０２）する。Next, a method of manufacturing the above-described electronic module will be described with reference to the flow chart of FIG. First, the state before the bare chip IC 1 is mounted on the electronic module shown in FIG. 1 is as shown in FIG. 2, and the heat resistant film 8 is placed so that the back surface of the opening A formed in the printed wiring board 5 is closed. It is stretched on the back surface of the printed wiring board 5. After this, the bare chip IC1 is die-mounted on the heat-resistant film 8 in the opening A (step 301). Next, bare chip IC1
An adhesive such as a die paste is filled with a dispenser between the side surface of the opening and the inner surface of the opening A (step 302).
【００１７】その後、このダイペーストを熱硬化（ステ
ップ３０３）して、ベアチップＩＣを開口孔Ａの側面に
接着して固定する。次にベアチップＩＣと回路パターン
６間を接続する金ワイヤー２などのワイヤボンディング
（ステップ３０４）を実施した後、ベアチップＩＣ１の
上部が覆われるように樹脂７による封止（ステップ３０
５）及びこの樹脂７の熱硬化（ステップ３０６）を行
う。次に、印刷配線板５の上面に張り付けてある耐熱性
フィルム８を剥離（ステップ３０７）し、実装完了とな
る。その後、ステップ３０８にてベアチップＩＣ１の動
作試験を行って電子モジュールの製造が終了する。Thereafter, the die paste is thermally cured (step 303), and the bare chip IC is bonded and fixed to the side surface of the opening A. Next, after wire bonding of the gold wire 2 or the like connecting the bare chip IC and the circuit pattern 6 is performed (step 304), sealing with the resin 7 is performed so that the upper part of the bare chip IC 1 is covered (step 30).
5) and thermal curing of the resin 7 (Step 306). Next, the heat resistant film 8 stuck on the upper surface of the printed wiring board 5 is peeled off (step 307), and the mounting is completed. Thereafter, in step 308, an operation test of the bare chip IC1 is performed, and the manufacture of the electronic module is completed.
【００１８】本実施の形態によれば、印刷配線板５に設
けられた開口孔Ａ内にベアチップＩＣ１を実装している
ため、印刷配線板５の厚みｔ分だけ、ベアチップＩＣ１
の実装厚みＴを小さくすることができ、厚み制約のマー
ジンを十分とることができる。従って、ＰＣカードモジ
ュールのように、その厚みに規制があった場合で、ベア
チップＩＣ１を上から封止する樹脂７の厚みを多少厚く
しても、ベアチップＩＣ１の実装厚みＴは上記規制を余
裕を持ってクリアーするため、樹脂７による封止工程を
容易にすることができると共に、顕微鏡検査及び高さ測
定及びリペアーなどの組立工数を削減すことができ、そ
の歩留まりを向上させて、電子モジュールの製造効率を
向上させることができる。これにより、高密度、薄板、
極小サイズの電子モジュールの製造コストを低減させる
ことができる。According to the present embodiment, since bare chip IC 1 is mounted in opening A provided in printed wiring board 5, bare chip IC 1 has a thickness t of printed wiring board 5.
Can be reduced, and the margin of the thickness constraint can be sufficiently secured. Therefore, when the thickness is restricted as in the case of a PC card module, the mounting thickness T of the bare chip IC 1 does not exceed the restriction even if the thickness of the resin 7 for sealing the bare chip IC 1 from above is somewhat increased. Since it can be held and cleared, the sealing process with the resin 7 can be facilitated, and the number of assembling steps such as microscopic inspection, height measurement and repair can be reduced, the yield can be improved, and Manufacturing efficiency can be improved. This allows high density, thin plates,
The manufacturing cost of an extremely small-sized electronic module can be reduced.
【００１９】[0019]
【発明の効果】以上記述した如く本発明の電子モジュー
ル及び電子モジュールの製造方法によれば、ベアチップ
ＩＣを印刷配線板に穿かれた凹部に収容して実装するこ
とにより、厚み規制がある電子モジュールにおいてもベ
アチップＩＣの実装を容易として、前記電子モジュール
の製造効率を向上させることができる。As described above, according to the electronic module and the method of manufacturing the electronic module of the present invention, the bare chip IC is accommodated in the concave portion formed in the printed wiring board and mounted, so that the electronic module having the thickness regulation is provided. Also, the mounting efficiency of the electronic module can be improved by easily mounting the bare chip IC.
【図１】本発明の電子モジュールの一実施の形態の構成
を示した断面図。FIG. 1 is a sectional view showing the configuration of an embodiment of an electronic module of the present invention.
【図２】ベアチップＩＣの実装前の印刷配線板を示した
断面図。FIG. 2 is a sectional view showing a printed wiring board before mounting a bare chip IC.
【図３】本発明の電子モジュールの製造方法を説明する
実装プロセスフローを示した図。FIG. 3 is a view showing a mounting process flow for explaining a method of manufacturing an electronic module of the present invention.
【図４】従来の電子モジュールの構成例を示した断面
図。FIG. 4 is a sectional view showing a configuration example of a conventional electronic module.
【図５】図４に示した電子モジュールの製造方法を説明
する実装プロセスフローを示した図。FIG. 5 is a view showing a mounting process flow for explaining a method of manufacturing the electronic module shown in FIG. 4;
１ ベアチップＩＣ ２ 金ワイヤー ３ 接着剤 ５ 印刷配線板 ６ パターン ７ 樹脂 ８ 耐熱性フィルム DESCRIPTION OF SYMBOLS 1 Bare chip IC 2 Gold wire 3 Adhesive 5 Printed wiring board 6 Pattern 7 Resin 8 Heat resistant film
Claims (5)
と、 この印刷配線板に穿かれた凹部と、 この凹部に収容されて前記印刷配線板に実装されたベア
チップとを具備することを特徴とする電子モジュール。1. A printed wiring board having a pattern formed on a surface thereof, a recess formed in the printed wiring board, and a bare chip accommodated in the recess and mounted on the printed wiring board. Electronic module.
から封止する樹脂を有することを特徴とする請求項１記
載の電子モジュール。2. The electronic module according to claim 1, further comprising a resin for sealing the bare chip housed in the recess from above.
ベアチップを実装して製造される電子モジュールの製造
方法において、 前記印刷配線板に凹部を穿ち、 この凹部に前記ベアチップを収容し、 この収容したベアチップを前記凹部に接着剤で接着して
固定した後ワイヤボンディングを施し、 更にこのベアチップの上部から樹脂封止を施すことを特
徴とする電子モジュールの製造方法。3. A method for manufacturing an electronic module, wherein a bare chip is mounted on a printed wiring board having a pattern formed on a surface thereof, wherein a recess is formed in the printed wiring board, and the bare chip is accommodated in the recess. A method of manufacturing an electronic module, comprising: bonding the bare chip to the concave portion with an adhesive, fixing the bare chip, performing wire bonding, and performing resin sealing from above the bare chip.
開口孔と、 この開口孔を裏側から塞ぐように前記印刷配線板の裏側
から張り付けられた耐熱性フィルムとにより構成され、 このような凹部に前記ベアチップを実装した後、前記耐
熱性フィルムを剥離することを特徴とする請求項３記載
の電子モジュールの製造方法。4. The recess is constituted by an opening formed in the printed wiring board, and a heat-resistant film adhered from the back side of the printed wiring board so as to cover the opening from the back side. 4. The method according to claim 3, wherein the heat-resistant film is peeled after mounting the bare chip in the concave portion.
ールであることを特徴とする請求項３又は４記載の電子
モジュールの製造方法。5. The method according to claim 3, wherein the electronic module is a PC card module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8326522A JPH10173085A (en) | 1996-12-06 | 1996-12-06 | Electronic module and manufacturing method of electronic module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8326522A JPH10173085A (en) | 1996-12-06 | 1996-12-06 | Electronic module and manufacturing method of electronic module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10173085A true JPH10173085A (en) | 1998-06-26 |
Family
ID=18188777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8326522A Withdrawn JPH10173085A (en) | 1996-12-06 | 1996-12-06 | Electronic module and manufacturing method of electronic module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10173085A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6683795B1 (en) | 2002-04-10 | 2004-01-27 | Amkor Technology, Inc. | Shield cap and semiconductor package including shield cap |
| US6747352B1 (en) | 2002-08-19 | 2004-06-08 | Amkor Technology, Inc. | Integrated circuit having multiple power/ground connections to a single external terminal |
| US6784534B1 (en) | 2002-02-06 | 2004-08-31 | Amkor Technology, Inc. | Thin integrated circuit package having an optically transparent window |
| US6995448B2 (en) | 2001-04-02 | 2006-02-07 | Amkor Technology, Inc. | Semiconductor package including passive elements and method of manufacture |
| US7042072B1 (en) | 2002-08-02 | 2006-05-09 | Amkor Technology, Inc. | Semiconductor package and method of manufacturing the same which reduces warpage |
-
1996
- 1996-12-06 JP JP8326522A patent/JPH10173085A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6995448B2 (en) | 2001-04-02 | 2006-02-07 | Amkor Technology, Inc. | Semiconductor package including passive elements and method of manufacture |
| US6784534B1 (en) | 2002-02-06 | 2004-08-31 | Amkor Technology, Inc. | Thin integrated circuit package having an optically transparent window |
| US6683795B1 (en) | 2002-04-10 | 2004-01-27 | Amkor Technology, Inc. | Shield cap and semiconductor package including shield cap |
| US7042072B1 (en) | 2002-08-02 | 2006-05-09 | Amkor Technology, Inc. | Semiconductor package and method of manufacturing the same which reduces warpage |
| US6747352B1 (en) | 2002-08-19 | 2004-06-08 | Amkor Technology, Inc. | Integrated circuit having multiple power/ground connections to a single external terminal |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040302 |