JPS58218130A - 混成集積回路 - Google Patents
混成集積回路Info
- Publication number
- JPS58218130A JPS58218130A JP57101013A JP10101382A JPS58218130A JP S58218130 A JPS58218130 A JP S58218130A JP 57101013 A JP57101013 A JP 57101013A JP 10101382 A JP10101382 A JP 10101382A JP S58218130 A JPS58218130 A JP S58218130A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring
- integrated circuit
- substrate
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
本発明は、混成集積回路、特に該混成集積回路基板上に
実装するICチップ構造の改良に関するものである。
実装するICチップ構造の改良に関するものである。
従来、この種の装置として第1図に示すものがあった。
図において、(1)は混成集積回路基板、(2)μ半導
体ウェハ上に回路を実装したICチップ、(3a)は該
チップ(2)上に形成された金属パッド、(3b)はポ
ンディング用ワイヤ、(4)は基板(1)上の配線であ
る。
体ウェハ上に回路を実装したICチップ、(3a)は該
チップ(2)上に形成された金属パッド、(3b)はポ
ンディング用ワイヤ、(4)は基板(1)上の配線であ
る。
従来の混成集積′回路用ICチップ(2)を混成回路基
板(1)上に配置する場合、該基板(1)上にICチッ
プ(2)を直接搭載し、該チップ(2)上の金属パッド
(3りと基板(1)上の配線(4)とをワイヤボンドし
、金属ワイヤ(3b)によシlCチップ(2)と配線(
4)とを接続するようにしている。このため該チップ(
2)の構造は第1図から理解できるようにウェハに片面
しか回路を実装できず、ウェハを有効利用していない。
板(1)上に配置する場合、該基板(1)上にICチッ
プ(2)を直接搭載し、該チップ(2)上の金属パッド
(3りと基板(1)上の配線(4)とをワイヤボンドし
、金属ワイヤ(3b)によシlCチップ(2)と配線(
4)とを接続するようにしている。このため該チップ(
2)の構造は第1図から理解できるようにウェハに片面
しか回路を実装できず、ウェハを有効利用していない。
またこのことが基板(1)の面積を増大させる原因にも
なっている。
なっている。
この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、半導体ウェハの両面に回路を実
装し、該ウェハの表面にはホンディング用の金属パッド
を形成し、裏面には混成集積回路基板上にICチップを
保持するとともに該基板上の配線と電気的に接続するた
めのハンダバンプを形成することによシ、ウェハを有効
利用でき、基板の面積を増大させずに高集積度化を達成
できる混成集積回路を提供することを目的としている。
ためになされたもので、半導体ウェハの両面に回路を実
装し、該ウェハの表面にはホンディング用の金属パッド
を形成し、裏面には混成集積回路基板上にICチップを
保持するとともに該基板上の配線と電気的に接続するた
めのハンダバンプを形成することによシ、ウェハを有効
利用でき、基板の面積を増大させずに高集積度化を達成
できる混成集積回路を提供することを目的としている。
以下、この発明の一実施例を図について説明する。
第2図は本発明の一実施例による混成集積回路の断面図
である。
である。
本発明による混成集積回路は、基板(5)に実装する半
導体ウニハチラグ(6)の両面に回路を実装し、それぞ
れの電気的接続のために表側に金属バット(6a) 、
裏側にハンダバンプ(6c)を形成したものである。
導体ウニハチラグ(6)の両面に回路を実装し、それぞ
れの電気的接続のために表側に金属バット(6a) 、
裏側にハンダバンプ(6c)を形成したものである。
両面に配& (71+81を施した混成集積回路基板(
5)に上記の構造のICチップ(6)が金属パッド(6
a)を上にして配置されている。lJチップ(6)の表
側はワイヤボンディングにより基板(5)の底側の配線
(7)に接続され、裏側のバンプ(6C)lはIcチッ
プ(6)を固′1 定するとともに、基板(2)の表側の配線(7りに接続
されている。なおこの配! (7a)はスルーホール(
8a)を介して基板(5)の裏側の配線(8)につなが
っているものである。
5)に上記の構造のICチップ(6)が金属パッド(6
a)を上にして配置されている。lJチップ(6)の表
側はワイヤボンディングにより基板(5)の底側の配線
(7)に接続され、裏側のバンプ(6C)lはIcチッ
プ(6)を固′1 定するとともに、基板(2)の表側の配線(7りに接続
されている。なおこの配! (7a)はスルーホール(
8a)を介して基板(5)の裏側の配線(8)につなが
っているものである。
なお、第2図に示す例では単層の基板を用いているが、
勿論多層の基板にも利用でき、この場合、よシ高集積度
な混成集積回路を実現できる。
勿論多層の基板にも利用でき、この場合、よシ高集積度
な混成集積回路を実現できる。
第3図は上記の様なICチップを重畳して用いる例を示
す。図において、(10)は基板(5)上に配置された
ICチップである。チップ00)の表側の回路はワイヤ
(10b)によシ基板(5)の表側の配線(7)と接続
され、裏側の回路はノ・ンダバンプ(IOC)により、
基板(5)の裏側の配線(8)につながっている配線(
7a)に接続されている。またICチップ(9)はチッ
プ叫の上に配置されておシ、両チップ+91 (10の
表側の回路は金属パッド(9aXtoa)およびワイヤ
(9b)を介して接続され、チップ’ +91の裏側の
回路は・・・ダ・・・プ(9C)および金属7配線(1
0d)によシチツプ00の表側の回路と接続され゛てい
る。このようにすれば立体的にICチップを□実装でき
、さらに高集積度な混成集積回路が実現可能となる。
す。図において、(10)は基板(5)上に配置された
ICチップである。チップ00)の表側の回路はワイヤ
(10b)によシ基板(5)の表側の配線(7)と接続
され、裏側の回路はノ・ンダバンプ(IOC)により、
基板(5)の裏側の配線(8)につながっている配線(
7a)に接続されている。またICチップ(9)はチッ
プ叫の上に配置されておシ、両チップ+91 (10の
表側の回路は金属パッド(9aXtoa)およびワイヤ
(9b)を介して接続され、チップ’ +91の裏側の
回路は・・・ダ・・・プ(9C)および金属7配線(1
0d)によシチツプ00の表側の回路と接続され゛てい
る。このようにすれば立体的にICチップを□実装でき
、さらに高集積度な混成集積回路が実現可能となる。
以上のように、この発明によれば半導体ウエノ・の両面
に回路を実装し、該ウエノ・の表面にはポンディング用
の金属パッドを形成し、裏面には混成集積回路基板にI
Cチップを保持するとともに該基板上の配線と電気的に
接続するためのノ・ンダノ(ンプを形成するようにした
ので、従来の片面しか利用しなかったICチップよシ、
チップをよシ効果的に利用でき、高集積度の混成集積回
路を小型化して得ることができる効果がある0
に回路を実装し、該ウエノ・の表面にはポンディング用
の金属パッドを形成し、裏面には混成集積回路基板にI
Cチップを保持するとともに該基板上の配線と電気的に
接続するためのノ・ンダノ(ンプを形成するようにした
ので、従来の片面しか利用しなかったICチップよシ、
チップをよシ効果的に利用でき、高集積度の混成集積回
路を小型化して得ることができる効果がある0
第1図は、従来のICチップを用いた混成集積回路の断
面図、第2図は本発明の一実施例による混成集積回路の
断面図、第3図は本発明の他の実施例による混成集積回
路の断面図である。 (61+91 (10)−I Cチップ、(6aX9a
X10a)−・・金楓ノ<ラド(6CX9cXlOc)
・・・ノ・ンダバンプ、(5)・・・基板、(7+ +
81・・・配線0 なお図中同一符号は同−又は相当部分を示す。 代 理 人 葛 野 信 −第1図 第2図 第3図
面図、第2図は本発明の一実施例による混成集積回路の
断面図、第3図は本発明の他の実施例による混成集積回
路の断面図である。 (61+91 (10)−I Cチップ、(6aX9a
X10a)−・・金楓ノ<ラド(6CX9cXlOc)
・・・ノ・ンダバンプ、(5)・・・基板、(7+ +
81・・・配線0 なお図中同一符号は同−又は相当部分を示す。 代 理 人 葛 野 信 −第1図 第2図 第3図
Claims (1)
- (1)混成集積回路基板と、半導体ウェハの両面に回路
が実装されたICチップと、このICチップの表面側に
形成された上記混成集積回路基板上の配線との間でワイ
ヤボンディングするための金属パッドと、上記ICチッ
プの裏・面側に形成され該ICチップを上記混成集積回
路基板上で保持するとともに該回路基板上の配線との間
で電気的接続を行なうだめのハンダバンプとを備えたこ
とを特徴とする混成集積回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57101013A JPS58218130A (ja) | 1982-06-11 | 1982-06-11 | 混成集積回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57101013A JPS58218130A (ja) | 1982-06-11 | 1982-06-11 | 混成集積回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58218130A true JPS58218130A (ja) | 1983-12-19 |
Family
ID=14289335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57101013A Pending JPS58218130A (ja) | 1982-06-11 | 1982-06-11 | 混成集積回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58218130A (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5703405A (en) * | 1993-03-15 | 1997-12-30 | Motorola, Inc. | Integrated circuit chip formed from processing two opposing surfaces of a wafer |
US6340845B1 (en) * | 1999-01-22 | 2002-01-22 | Nec Corporation | Memory package implementing two-fold memory capacity and two different memory functions |
US6472738B2 (en) | 2000-09-08 | 2002-10-29 | Fujitsu Quantum Devices Limited | Compound semiconductor device |
US6706557B2 (en) | 2001-09-21 | 2004-03-16 | Micron Technology, Inc. | Method of fabricating stacked die configurations utilizing redistribution bond pads |
US8102038B2 (en) * | 2009-09-18 | 2012-01-24 | Texas Instruments Incorporated | Semiconductor chip attach configuration having improved thermal characteristics |
-
1982
- 1982-06-11 JP JP57101013A patent/JPS58218130A/ja active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5703405A (en) * | 1993-03-15 | 1997-12-30 | Motorola, Inc. | Integrated circuit chip formed from processing two opposing surfaces of a wafer |
US6340845B1 (en) * | 1999-01-22 | 2002-01-22 | Nec Corporation | Memory package implementing two-fold memory capacity and two different memory functions |
US6472738B2 (en) | 2000-09-08 | 2002-10-29 | Fujitsu Quantum Devices Limited | Compound semiconductor device |
US6706557B2 (en) | 2001-09-21 | 2004-03-16 | Micron Technology, Inc. | Method of fabricating stacked die configurations utilizing redistribution bond pads |
US6847105B2 (en) * | 2001-09-21 | 2005-01-25 | Micron Technology, Inc. | Bumping technology in stacked die configurations |
US8102038B2 (en) * | 2009-09-18 | 2012-01-24 | Texas Instruments Incorporated | Semiconductor chip attach configuration having improved thermal characteristics |
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