JPS5820159B2 - Method for manufacturing thin film circuit board with cross wiring - Google Patents
Method for manufacturing thin film circuit board with cross wiringInfo
- Publication number
- JPS5820159B2 JPS5820159B2 JP49105838A JP10583874A JPS5820159B2 JP S5820159 B2 JPS5820159 B2 JP S5820159B2 JP 49105838 A JP49105838 A JP 49105838A JP 10583874 A JP10583874 A JP 10583874A JP S5820159 B2 JPS5820159 B2 JP S5820159B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film conductor
- thick film
- conductor layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は交叉配線を有する薄膜回路基板の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a thin film circuit board having cross wiring.
従来の薄膜回路基板は二次元であるために、配線が交叉
する場合は基板に設けられた穴を利用してジャンパ線を
用いる方法やワイヤボンディングにより配線する方法が
取られている。Conventional thin-film circuit boards are two-dimensional, so when wiring intersects, a method of using jumper wires using holes provided in the board or a method of wiring by wire bonding is used.
しかしながら、近年電子機器の高性能化、多様化に伴い
回路が複雑化し、配線の交叉が増加するとともに小型化
、高信頼性が要求されるようになり、従来のジャンパ線
を用いる方法やワイヤボンディングにより配線する方法
では限界があった。However, in recent years, as electronic devices have become more sophisticated and diversified, circuits have become more complex, the number of wiring crossings has increased, and miniaturization and high reliability have become required. There were limits to the wiring method.
この問題を解決するために配線の交叉を実現する方法と
して更にエアギャップクロスオーバやボンディッドクロ
スオーバなどが考えられているが、後者は作業性が悪く
マスク設計上の制約が太き（、前者は経済的に引き合わ
ない等の欠点を有している。In order to solve this problem, air-gap crossovers and bonded crossovers are being considered as methods to realize wiring crossovers, but the latter has poor workability and has severe restrictions on mask design (the former has disadvantages such as not being economically viable.
その他の方法も考えられているがそれぞれ固有の欠点を
有する。Other methods have been considered, but each has its own drawbacks.
本発明は、上記欠点を解消するためになされたものであ
り、その目的とするところは、厚膜導電体、及び厚膜絶
縁層を利用することにより製造が容易で、しかも高信頼
度の交叉配線を有する薄膜回路基板を提供することにあ
る。The present invention was made in order to eliminate the above-mentioned drawbacks, and its purpose is to provide a highly reliable crossover that is easy to manufacture by using a thick film conductor and a thick film insulating layer. An object of the present invention is to provide a thin film circuit board having wiring.
また他の目的は外部リードを含むすべての搭載部分を熱
圧着により高信頼度で接続できる交叉配線を有する薄膜
回路基板を提供することにある。Another object of the present invention is to provide a thin film circuit board having crossover wiring that allows all mounting parts including external leads to be connected with high reliability by thermocompression bonding.
本発明の特徴は、絶縁基板上に厚膜導電体ペーストによ
り所望パターンの厚膜導電体層を形成する工程と、この
厚膜導電体層の一部分を除いて厚膜絶縁体層を形成する
工程と、この厚膜絶縁体層から露出したこの厚膜導電体
部を除（基板全面に薄膜絶縁体層を被着する工程と、更
にこの基板全面に薄膜導電体層を被着する工程と、この
厚膜絶縁体層上においてこの厚膜導電体と立体的に交叉
するような所望の回路パターンにこの薄膜導電体層をエ
ツチング除去する工程とを含む交叉配線を有する薄膜回
路基板の製造方法にある。The features of the present invention include a step of forming a thick film conductor layer with a desired pattern on an insulating substrate using a thick film conductor paste, and a step of forming a thick film insulator layer by excluding a part of the thick film conductor layer. and removing the thick film conductor portion exposed from the thick film insulator layer (a step of depositing a thin film insulator layer over the entire surface of the substrate, and a step of depositing a thin film conductor layer over the entire surface of the substrate, A method for manufacturing a thin film circuit board having cross wiring, which includes the step of etching and removing the thin film conductor layer to form a desired circuit pattern that three-dimensionally intersects with the thick film conductor on the thick film insulator layer. be.
以下図面を参照して、本発明の具体的実施例を詳細に説
明する。Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明の方法に基いて、形成された交叉配線を
含む薄膜回路基板の平面図であり、第２図乃至第６図ま
では第１図の薄膜回路基板の製造工程順を示す断面図で
あり、１はセラミック基板２は厚膜導電体層、３は厚膜
絶縁体層、４′は酸化タンタル膜、５は窒化タンタル膜
、６は薄膜導電体層である。FIG. 1 is a plan view of a thin film circuit board including cross wiring formed according to the method of the present invention, and FIGS. 2 to 6 show the order of manufacturing steps for the thin film circuit board of FIG. 1. In the cross-sectional view, 1 is a ceramic substrate 2 which is a thick film conductor layer, 3 is a thick film insulator layer, 4' is a tantalum oxide film, 5 is a tantalum nitride film, and 6 is a thin film conductor layer.
本発明の薄膜回路基板の製造方法としては、まず、第２
図に示すように薄膜素子を形成しようとするセラミック
基板１の上に、交叉する配線のうち、一方の配線の交叉
部分を厚膜導電体ペーストを印刷、焼成することにより
厚膜導電体層２を形成する。As a method for manufacturing a thin film circuit board of the present invention, first, the second
As shown in the figure, a thick film conductor layer 2 is formed on a ceramic substrate 1 on which a thin film element is to be formed by printing and baking a thick film conductor paste on the crossing portion of one of the intersecting wirings. form.
この厚膜導電体層上にガラス等の絶縁ペーストを印刷、
焼成して厚膜絶縁体層３を形成する。Printing an insulating paste such as glass on this thick film conductor layer,
The thick film insulator layer 3 is formed by firing.
この時、厚膜導電体層２が絶縁体層３から０．２朋乃至
Ｑ、 ３ ｍ７ｆｔ程度露出するように形成する。At this time, the thick film conductor layer 2 is formed so as to be exposed from the insulator layer 3 by about 0.2 mm to 3 m and 7 ft.
次に第３図に示すように、基板全面にスパッタリングに
より５００乃至１０００オングストロームの厚さでタン
タル膜４を被着する。Next, as shown in FIG. 3, a tantalum film 4 with a thickness of 500 to 1000 angstroms is deposited over the entire surface of the substrate by sputtering.
このタンタル膜はボンディング性のよいベータタンタル
の結晶構造が好ましい。This tantalum film preferably has a beta-tantalum crystal structure with good bonding properties.
続いて周知のホトレジスト技術を用いて絶縁体層から露
出した厚膜導電体層上のタンタル膜をエツチングにより
除去する。Subsequently, the tantalum film on the thick film conductor layer exposed from the insulator layer is removed by etching using a well-known photoresist technique.
その時用いられる典型的なエツチング液としてはフッ酸
と、硝酸の混合液がある。A typical etching solution used at this time is a mixture of hydrofluoric acid and nitric acid.
次に５００℃乃至６００℃の温度で５時間前後加熱して
基板上に残っているタンタル膜を熱的に酸化させて第４
図に示す酸化タンタル膜４′を形成する。Next, the tantalum film remaining on the substrate is thermally oxidized by heating at a temperature of 500°C to 600°C for about 5 hours, and the fourth
A tantalum oxide film 4' shown in the figure is formed.
この酸化タンタル膜は相続く処理工程中で、エツチング
液から基板を保護する役割を果す。This tantalum oxide film serves to protect the substrate from the etching solution during subsequent processing steps.
基板面は、絶縁体層から露出した厚膜導電体層以外すべ
て酸化タンタル膜で覆われており、露出した厚膜導電体
層は後で被着する薄膜導電体層とのコンタクトを形成す
る。The surface of the substrate is covered with a tantalum oxide film on all but the thick film conductor layer exposed from the insulator layer, and the exposed thick film conductor layer forms a contact with a later deposited thin film conductor layer.
次に第５図に示すように通常の薄膜回路基板と同一条件
で薄膜抵抗体となる窒化タンタルなどの金属５をスパッ
タリングで被着し続いて薄膜導電体層６を蒸着により被
着する。Next, as shown in FIG. 5, a metal 5 such as tantalum nitride, which will become a thin film resistor, is deposited by sputtering under the same conditions as for a normal thin film circuit board, and then a thin film conductor layer 6 is deposited by vapor deposition.
通常薄膜導電体層としては熱圧着ボンディングの接合強
度の点から２乃至３種類の金属を重ねて被着している。Usually, the thin film conductor layer is made by depositing two or three kinds of metals in a layered manner from the viewpoint of the bonding strength of thermocompression bonding.
次に選択エツチングにより薄膜導電体層及びメンタル薄
膜抵抗のパターン形成を行うことにより第６図に示すよ
うな交叉配線を有する薄膜回路基板が形成される。Next, by patterning a thin film conductor layer and a mental thin film resistor by selective etching, a thin film circuit board having cross wiring as shown in FIG. 6 is formed.
このパターン形成６同知のいづれかの手法を用いても形
成できる。This pattern formation 6 can also be formed using any known method.
第６図のパターンを真上から見たのが第１図であり、左
から抵抗体部、交叉配線部外部端子パット部を示す。FIG. 1 shows the pattern of FIG. 6 viewed from directly above, showing from the left a resistor portion, a cross wiring portion, and an external terminal pad portion.
配線の交叉部分について見ると抵抗体の一端からの薄膜
導電体配線は酸化タンタルにあけられた穴を通して厚膜
導電体層２の一端に接続され厚膜導電体層を通してもう
一端に接続された薄膜導電体配線に接続される。Looking at the intersection of the wiring, the thin film conductor wiring from one end of the resistor is connected to one end of the thick film conductor layer 2 through a hole made in tantalum oxide, and the thin film conductor wiring is connected to the other end through the thick film conductor layer. Connected to conductor wiring.
つまり薄膜導電体−窒化タンタル−厚膜導電体−窒化タ
ンタル−薄膜導電体となる。In other words, it becomes a thin film conductor-tantalum nitride-thick film conductor-tantalum nitride-thin film conductor.
これと交叉する配線は絶縁体層を介して下の厚膜導電体
と交叉して薄膜導電体だけで配線される。Wiring that intersects this is wired using only the thin film conductor, crossing the underlying thick film conductor via the insulator layer.
以上、本発明の一実施例である交叉配線を有する薄膜回
路基板の製造工程にわたって説明した。The manufacturing process of a thin film circuit board having cross wiring, which is an embodiment of the present invention, has been described above.
なお、上記実施例では厚膜導電体層と、厚膜絶縁体層を
別々に焼成して形成しているが同時に焼成して形成する
ことも可能であることは言うまでもない。In the above embodiments, the thick film conductor layer and the thick film insulator layer are formed by firing separately, but it goes without saying that they can be fired at the same time.
また本実施例においては薄膜抵抗体層を同時に形成する
場合について述べたがこの薄膜抵抗体層は本発明の必須
要件ではない。Further, in this embodiment, a case has been described in which a thin film resistor layer is formed at the same time, but this thin film resistor layer is not an essential requirement of the present invention.
更に本発明の応用例としては、隣接して複数の交叉配線
が存在する場合には第７図に示すようスルーホールＴを
利用して交叉部分を形成することも可能である。Furthermore, as an application example of the present invention, when there are a plurality of adjacent crossing wires, it is also possible to form the crossing portions using through holes T as shown in FIG.
以上述べた本発明によれば次のような特徴及び効果が得
られる。According to the present invention described above, the following features and effects can be obtained.
（１）通常の薄膜回路基板に厚膜導電体層と、厚膜絶縁
体層の形成工程が加わるだけであり、製造が非常に単純
かつ容易である。(1) Manufacturing is very simple and easy, as only the steps of forming a thick film conductor layer and a thick film insulator layer are added to a normal thin film circuit board.
（２）厚膜導電体層、厚膜絶縁体層の形成は、製造工程
の最初に行うため後で形成する薄膜導電体、薄膜抵抗体
に一切悪影響を及ぼすことはない。(2) Since the formation of the thick film conductor layer and the thick film insulator layer is performed at the beginning of the manufacturing process, there is no adverse effect on the thin film conductor and thin film resistor that are formed later.
（３）交叉配線間の絶縁体として厚膜絶縁体層を利用し
ているために、絶縁の信頼性が高く機械的にも強く、交
叉配線間の容量も少ない。(3) Since a thick film insulator layer is used as an insulator between the crossover wirings, the insulation is highly reliable and mechanically strong, and the capacitance between the crossover wirings is small.
（４）ボンディング、半田デイツプ抵抗調節など薄膜回
路基板で可能なことは総て本発明による基板においても
可能である。(4) All of the things that are possible with thin film circuit boards, such as bonding and solder dip resistance adjustment, are also possible with the board according to the present invention.
第１図は本発明による方法で形成した交叉配線を有する
薄膜回路基板の平面図であり、第２図乃至第６図は第１
図の薄膜回路基板の製造工程順に示した断面図である。
第７図は、スルーホールにより交叉配線を形成した場合
の断面図である。
なお、図において、１・・・・・・セラミック基板、２
・・・・・・厚膜導電体層、３・・・・・・厚膜絶縁体
層、４・・・・・・ベータタンタル、４′・・・・・・
酸化タンタル膜、５・・・・・・窒化タンタル膜、６・
・・・・・薄膜導電体層、である。FIG. 1 is a plan view of a thin film circuit board having cross wiring formed by the method according to the present invention, and FIGS.
FIG. 2 is a cross-sectional view showing the manufacturing process of the thin film circuit board shown in the figure. FIG. 7 is a cross-sectional view when cross wiring is formed using through holes. In addition, in the figure, 1...ceramic substrate, 2
...Thick film conductor layer, 3...Thick film insulator layer, 4...Beta tantalum, 4'...
Tantalum oxide film, 5... Tantalum nitride film, 6.
...Thin film conductor layer.
Claims (1)
ンの厚膜導電体層を形成する工程と、該厚膜導電体層の
一部分を除いて厚膜絶縁体層を形成する工程と、該厚膜
絶縁体層から露出した該厚膜導電体部を除く基板全面に
薄膜絶縁体層を被着する工程と、更に該基板全面に薄膜
導電体層を被着する工程と、該厚膜導電体層上目ルク該
厚膜導電体と立体的に交叉するような所望の回路パター
ンに該薄膜導電体層をエツチング除去する工程とを含む
ことを特徴とする交叉配線を有する薄膜回路基板の製造
方法。1. A step of forming a thick film conductor layer with a desired pattern on an insulating substrate using a thick film conductor paste, a step of forming a thick film insulator layer excluding a part of the thick film conductor layer, a step of depositing a thin film insulator layer over the entire surface of the substrate except for the thick film conductor portion exposed from the insulator layer; a step of further depositing a thin film conductor layer over the entire surface of the substrate; and a step of depositing the thin film conductor layer over the entire surface of the substrate. 1. A method for manufacturing a thin film circuit board having cross wiring, the method comprising the step of etching away the thin film conductor layer to form a desired circuit pattern that three-dimensionally intersects with the thick film conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49105838A JPS5820159B2 (en) | 1974-09-13 | 1974-09-13 | Method for manufacturing thin film circuit board with cross wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49105838A JPS5820159B2 (en) | 1974-09-13 | 1974-09-13 | Method for manufacturing thin film circuit board with cross wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5132954A JPS5132954A (en) | 1976-03-19 |
| JPS5820159B2 true JPS5820159B2 (en) | 1983-04-21 |
Family
ID=14418159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49105838A Expired JPS5820159B2 (en) | 1974-09-13 | 1974-09-13 | Method for manufacturing thin film circuit board with cross wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5820159B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536697B2 (en) * | 1983-03-10 | 1993-05-31 | Kanazawa Kogyo Kk |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5895668U (en) * | 1981-12-22 | 1983-06-29 | 松下電器産業株式会社 | printed wiring board |
| WO2018117111A1 (en) * | 2016-12-21 | 2018-06-28 | 大日本印刷株式会社 | Through electrode substrate, semiconductor device and method for producing through electrode substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4852185A (en) * | 1971-10-29 | 1973-07-21 | ||
| JPS4879987A (en) * | 1972-01-28 | 1973-10-26 | ||
| JPS494994A (en) * | 1972-04-27 | 1974-01-17 |
-
1974
- 1974-09-13 JP JP49105838A patent/JPS5820159B2/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4852185A (en) * | 1971-10-29 | 1973-07-21 | ||
| JPS4879987A (en) * | 1972-01-28 | 1973-10-26 | ||
| JPS494994A (en) * | 1972-04-27 | 1974-01-17 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536697B2 (en) * | 1983-03-10 | 1993-05-31 | Kanazawa Kogyo Kk |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5132954A (en) | 1976-03-19 |
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