JPH08222626A - Forming method for electrode pad - Google Patents

Forming method for electrode pad

Info

Publication number
JPH08222626A
JPH08222626A JP2180695A JP2180695A JPH08222626A JP H08222626 A JPH08222626 A JP H08222626A JP 2180695 A JP2180695 A JP 2180695A JP 2180695 A JP2180695 A JP 2180695A JP H08222626 A JPH08222626 A JP H08222626A
Authority
JP
Japan
Prior art keywords
forming
wiring
parts
electrode pad
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2180695A
Other languages
Japanese (ja)
Other versions
JP3702480B2 (en
Inventor
Koji Asaji
康志 浅地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2180695A priority Critical patent/JP3702480B2/en
Publication of JPH08222626A publication Critical patent/JPH08222626A/en
Application granted granted Critical
Publication of JP3702480B2 publication Critical patent/JP3702480B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Abstract

PURPOSE: To form electrode pads having high electric reliability by short- circuiting a plurality of wiring parts via conductors to an equipotential, forming the pads at the predetermined parts of the wiring parts by electroless plating, then removing at least the parts of the conductor, and insulating the pads from each other. CONSTITUTION: A plurality of wiring parts 2 are formed on the surface of a semiconductor substrate 1, the parts of the parts 2 are short-circuited via conductors 7, 8 to an equipotential. Then, after electrode pads 6 are formed at predetermined parts of the parts 2 by electroless plating, at least the parts of the parts 7, 8 are removed, and the pads 6 are insulated from each other. For example, leads 7 are extended from the aluminum parts of the parts 2, and connected to a common lead 8. A zinc substituted part 5 is formed on the aluminum surface of the part 2 exposed via the opening 4, metal such as nickel or copper is precipitated on the surface of the part 5 to form the pads 6, and then leads 7 are cut.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、プリント基板やアルミ
ナ基板等との接続に用いるために半導体回路の表面部分
に形成する電極パッドの形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an electrode pad formed on the surface of a semiconductor circuit for use in connection with a printed board, an alumina board or the like.

【０００２】[0002]

【従来の技術】種々の機能を有する受動素子や能動素子
等の多数の回路素子および、各種回路素子を相互に接続
する配線部とから構成された半導体回路においては、配
線部の所定の表面部分には電極パッドが形成される。こ
の半導体回路は、形成された電極パッドを介して、半田
バンプを用いた接続方法や、ワイヤ−ボンディングによ
る接続方法や、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ
Ｂｏｎｄｉｎｇ）による接続方法により、プリント基
板やアルミナ基板等と電気的に接続される。2. Description of the Related Art In a semiconductor circuit composed of a large number of circuit elements having various functions such as passive elements and active elements, and a wiring section for interconnecting various circuit elements, a predetermined surface portion of the wiring section An electrode pad is formed on the. This semiconductor circuit has a connection method using solder bumps, a connection method by wire bonding, and a TAB (Tape Automated) via the formed electrode pads.
It is electrically connected to a printed circuit board, an alumina substrate, or the like by a bonding method using bonding.

【０００３】図３（ａ）乃至（ｃ）を用いて、従来の電
極パッドの形成方法を説明する。A conventional method of forming an electrode pad will be described with reference to FIGS. 3 (a) to 3 (c).

【０００４】図３（ａ）のように、シリコン、ゲルマニ
ウム等の半導体基板１には、各種回路素子Ｅがイオン拡
散等の手段を用いて形成され、また半導体基板１の表面
には各種回路素子Ｅを相互に接続するための配線部２が
形成される。一般的に、配線部２は、所定形状のマスク
パタ−ンを用いて、半導体基板１の表面にアルミニウム
を蒸着、スパッタリング等することによって形成され
る。さらに、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ
Ｄｅｐｏｓｉｔｉｏｎ）法を用いて、配線部２の上か
ら、窒化シリコン膜あるいは酸化シリコン膜等の絶縁層
３を成膜する。この後、例えばフォトリソグラフィ技術
および異方性エッチング技術を用いて、窒化シリコン膜
あるいは酸化シリコン膜等の一部を除去して開口部４を
形成し、配線部２の所定位置のアルミニウム表面を露出
させる。フォトリソグラフィ技術とは、基板の表面にフ
ォトレジスト膜を塗布した後、所定マスクを用いてフォ
トレジスト膜を露光、現像し、エッチングを施したい基
板の表面部分のフォトレジスト膜を除去して、所定パタ
−ンのレジストマスクを形成する方法である。異方性エ
ッチング技術とは、一定方向には基板がエッチングされ
やすいが、他の方向にはエッチングされずらいという性
質を利用して行うエッチング方法である。As shown in FIG. 3A, various circuit elements E are formed on a semiconductor substrate 1 made of silicon, germanium or the like by means such as ion diffusion, and various circuit elements are formed on the surface of the semiconductor substrate 1. A wiring portion 2 for connecting E to each other is formed. Generally, the wiring portion 2 is formed by vapor-depositing aluminum on the surface of the semiconductor substrate 1 by using a mask pattern having a predetermined shape, sputtering, or the like. Furthermore, CVD (Chemical Vapor)
Deposition method is used to form an insulating layer 3 such as a silicon nitride film or a silicon oxide film on the wiring portion 2. After that, the opening 4 is formed by removing a part of the silicon nitride film or the silicon oxide film by using, for example, the photolithography technique and the anisotropic etching technique, and the aluminum surface at a predetermined position of the wiring portion 2 is exposed. Let The photolithography technique is to apply a photoresist film on the surface of a substrate, then expose and develop the photoresist film using a predetermined mask, remove the photoresist film on the surface portion of the substrate to be etched, This is a method of forming a pattern resist mask. The anisotropic etching technique is an etching method performed by utilizing the property that the substrate is easily etched in a certain direction but is not easily etched in other directions.

【０００５】次に、無電解メッキの一種である亜鉛置換
（ジンケ−ト）処理を行い、配線部２のアルミニウム表
面と亜鉛置換処理剤とを反応させる。なお、亜鉛置換処
理剤と絶縁層４とは反応しない。この結果、開口部４に
よって露出した配線部２のアルミニウム表面のみが亜鉛
と置換して、図３（ｂ）のように、亜鉛置換部５が形成
される。Next, a zinc substitution (zincate) treatment, which is a type of electroless plating, is performed to react the aluminum surface of the wiring portion 2 with the zinc substitution treatment agent. The zinc substitution treatment agent and the insulating layer 4 do not react. As a result, only the aluminum surface of the wiring part 2 exposed by the opening 4 is replaced with zinc, and the zinc replacement part 5 is formed as shown in FIG. 3B.

【０００６】さらに、無電解メッキ処理を行い、半田の
濡れ性の良いニッケルあるいは銅等の金属を亜鉛置換部
５の表面に析出させて、図３（ｃ）のように、電極パッ
ド６を形成する。Further, an electroless plating process is performed to deposit a metal such as nickel or copper having good solder wettability on the surface of the zinc-substituted portion 5 to form an electrode pad 6 as shown in FIG. 3 (c). To do.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、半導体
回路においては、不純物の濃度差を利用して形成した各
種回路素子Ｅが存在するため、形成した亜鉛置換部５の
それぞれの電位は一定とならない。このため、無電解メ
ッキによって亜鉛置換部５および電極パッド６を形成す
る際に、亜鉛置換部５における亜鉛の析出量や電極パッ
ド６における金属の析出量が一定せず、さらに析出状態
にばらつきが生じるため、膜厚や電気的特性が一定しな
いという欠点があった。However, in the semiconductor circuit, since there are various circuit elements E formed by utilizing the difference in concentration of impurities, the respective potentials of the formed zinc substitution parts 5 are not constant. Therefore, when the zinc replacement part 5 and the electrode pad 6 are formed by electroless plating, the amount of zinc deposited on the zinc replacement part 5 and the amount of metal deposited on the electrode pad 6 are not constant, and the deposition state varies. Since it occurs, there is a drawback that the film thickness and electrical characteristics are not constant.

【０００８】そこで、本発明は、電気的信頼性の高い電
極パッドを形成することを目的とする。Therefore, an object of the present invention is to form an electrode pad having high electrical reliability.

【０００９】[0009]

【課題を解決するための手段】本発明は、上記目的を達
成するために、次のような工程からなる。すなわち、第
一に、半導体基板の表面に複数の配線部を形成する工程
と、前記配線部の一部分を導体部を介して相互に短絡し
て等電位にする工程と、前記配線部の所定部分に無電解
メッキによって電極パッドを形成する工程と、前記導体
部の少なくとも一部分を除いて電極パッドを相互に絶縁
する工程とからなり、第二に、半導体基板の表面に、配
線部と、該配線部の所定部分から引き出されるリ−ド線
と、該リ−ド線に接続された共通導線を形成する工程
と、前記配線部の所定部分を露出する開口部を有した絶
縁層を形成する工程と、前記開口部によって露出した前
記配線部の所定部分に無電解メッキによって金属を析出
させる工程と、前記リ−ド線を切断する工程とからな
り、第三に、半導体基板の表面に配線部を形成する工程
と、前記配線部の所定部分を露出する複数の開口部を有
した絶縁層を形成する工程と、前記絶縁層の表面に、前
記開口部間の露出した配線部を短絡する金属層を形成す
る工程と、前記開口部を埋める前記金属層の表面部分を
露出する開口部を有するレジストマスクを形成する工程
と、該レジストマスクの開口部によって露出した前記金
属層の表面に金属を析出させる工程と、前記レジストマ
スクを除去するとともに、析出した金属部分以外の金属
層を除去する工程とからなるものである。In order to achieve the above object, the present invention comprises the following steps. That is, first, a step of forming a plurality of wiring portions on the surface of a semiconductor substrate, a step of short-circuiting a portion of the wiring portions to each other via a conductor portion to make them equipotential, and a predetermined portion of the wiring portion. A step of forming electrode pads by electroless plating, and a step of insulating the electrode pads from each other except at least a part of the conductor portion. Secondly, a wiring portion and a wiring portion on the surface of the semiconductor substrate. Forming a lead wire extending from a predetermined portion of the wiring part, a common conductor connected to the lead wire, and forming an insulating layer having an opening exposing the predetermined portion of the wiring portion. And a step of depositing a metal by electroless plating on a predetermined portion of the wiring portion exposed by the opening, and a step of cutting the lead wire. Thirdly, the wiring portion is formed on the surface of the semiconductor substrate. And a step of forming A step of forming an insulating layer having a plurality of openings for exposing a predetermined portion of the line portion, and a step of forming a metal layer on the surface of the insulating layer, which short-circuits the exposed wiring portion between the openings. Forming a resist mask having an opening exposing a surface portion of the metal layer filling the opening; depositing a metal on the surface of the metal layer exposed by the opening of the resist mask; The process comprises removing the mask and removing the metal layer other than the deposited metal portion.

【００１０】[0010]

【作用】第一の発明では、配線部の一部分は導部によっ
て相互に短絡されるので等電位となる。この結果、配線
部の所定部分に無電解メッキを行うと、この配線部の所
定部分の表面には均一な電極パッドが形成される。この
後、導体部の少なくとも一部を除くことにより電極パッ
ドの絶縁を行なう。In the first aspect of the present invention, a part of the wiring portion is short-circuited to each other by the conducting portion, so that they have the same potential. As a result, when electroless plating is performed on a predetermined portion of the wiring portion, uniform electrode pads are formed on the surface of the predetermined portion of the wiring portion. After that, the electrode pad is insulated by removing at least a part of the conductor portion.

【００１１】第二の発明では、配線部は、それぞれから
リ−ド線が引き出されて共通導線に接続されるので、短
絡されて同電位となる。この結果、絶縁膜に設けられた
開口部によって露出した配線部に無電解メッキを行う
と、この配線部の表面には均一に金属が析出する。この
後、リ−ド線を切断して、この配線部間の絶縁を行な
う。In the second aspect of the present invention, the lead portions of the wiring portions are drawn out from the respective wiring portions and connected to the common conducting wire. Therefore, the wiring portions are short-circuited to have the same potential. As a result, when electroless plating is performed on the wiring portion exposed by the opening provided in the insulating film, metal is uniformly deposited on the surface of the wiring portion. After that, the lead wire is cut to insulate the wiring portions.

【００１２】第三の発明では、絶縁膜に設けられた開口
部によって露出した配線部のアルミニウム部分を相互に
接続する金属層を絶縁膜の上に設けたので、開口部によ
って露出した配線部のアルミニウム部分は短絡され、同
電位となる。さらに、フォトレジストマスクを用いて、
開口部を埋める金属層の表面部分に、無電解メッキを行
なうと、この金属表面部分には均一に金属が析出する。
この後、レジストを除去し、析出した金属部分以外の金
属層をエッチング除去して、析出した金属部分の絶縁を
行なう。In the third invention, since the metal layer for connecting the aluminum portions of the wiring portion exposed by the opening provided in the insulating film to each other is provided on the insulating film, the wiring layer exposed by the opening is formed. The aluminum portion is short-circuited and has the same potential. Furthermore, using a photoresist mask,
When electroless plating is performed on the surface portion of the metal layer that fills the opening, metal is uniformly deposited on the surface portion of the metal.
After that, the resist is removed, and the metal layer other than the deposited metal portion is removed by etching to insulate the deposited metal portion.

【００１３】[0013]

【実施例】【Example】

（実施例１）図１（ａ）乃至（ｃ）を用いて、本発明に
かかる電極パッドの形成方法について説明する。なお、
本実施例は、配線部２としてアルミニウムを使用した場
合について説明する。従来の形成方法と同様の方法につ
いては説明を簡略化し、同じ構成部分については同じ番
号を使用する。(Embodiment 1) A method for forming an electrode pad according to the present invention will be described with reference to FIGS. In addition,
In this embodiment, a case where aluminum is used as the wiring portion 2 will be described. The description of the same method as the conventional forming method is simplified, and the same numbers are used for the same components.

【００１４】従来の形成方法と同様に、図１（ａ）のよ
うに、半導体基板１には、各種回路素子Ｅが形成され
る。また半導体基板１の表面には、各種回路素子Ｅを相
互に接続するためにアルミニウムの配線部２が形成され
る。ここで、従来の形成方法と異なる点は、後述する開
口部４によって露出する配線部２のアルミニウム部分の
それぞれからはリ−ド線７が引き出され、半導体回路が
形成された部分を囲むように、半導体基板１の表面に形
成された共通導線８に接続されていることである。この
結果、開口部４によって露出した配線部２のアルミニウ
ム部分は、短絡されて等電位となる。なお、リ−ド線７
および共通導線８は、配線部２と同じ方法で、同時に形
成される。Similar to the conventional forming method, various circuit elements E are formed on the semiconductor substrate 1 as shown in FIG. On the surface of the semiconductor substrate 1, aluminum wiring portions 2 for connecting various circuit elements E to each other are formed. Here, the difference from the conventional forming method is that the lead wire 7 is drawn out from each of the aluminum portions of the wiring portion 2 exposed by the openings 4 described later so as to surround the portion where the semiconductor circuit is formed. , Is connected to a common conductor 8 formed on the surface of the semiconductor substrate 1. As a result, the aluminum portion of the wiring portion 2 exposed by the opening 4 is short-circuited and becomes equipotential. In addition, lead wire 7
And the common conductor 8 is formed at the same time in the same method as the wiring part 2.

【００１５】さらに、窒化シリコン膜あるいは酸化シリ
コン膜等からなる絶縁層３が形成され、この絶縁層３に
は配線部２の所定位置の表面を露出させるための開口部
４が形成される。Further, an insulating layer 3 made of a silicon nitride film or a silicon oxide film is formed, and an opening 4 for exposing the surface of the wiring portion 2 at a predetermined position is formed in the insulating layer 3.

【００１６】次に、従来の方法と同様に、開口部４によ
って露出した配線部２のアルミニウム表面に、無電解メ
ッキの一種である亜鉛置換（ジンケ−ト）処理を行い、
亜鉛置換部５を形成する。この亜鉛置換部５だけでも電
極パッドとして使用することもできる。しかしながら、
この電極パッドを介して半導体基板１とプリント基板や
アルミナ基板等と接続する際の密着性を向上させるため
に、一般的にはさらに無電解メッキ処理を行い、図１
（ｃ）のように、ニッケルあるいは銅等の金属を亜鉛置
換部５の表面に析出させ、電極パッド６を形成する。亜
鉛置換処理および亜鉛置換部５の表面に無電解メッキを
する際に、亜鉛置換部５は等電位であるために金属が均
一に析出し、膜厚、膜質が極めてそろった電極パッド６
が形成される。この後、それぞれの電極パッド６の電気
的絶縁を行なうため、半導体回路の周縁部に設けられた
共通導線８と接続されたリ−ド線７を、絶縁層３の上か
ら切断する。Then, similarly to the conventional method, the aluminum surface of the wiring portion 2 exposed by the opening 4 is subjected to zinc substitution (zincate) treatment, which is a type of electroless plating,
The zinc substitution part 5 is formed. The zinc replacement portion 5 alone can be used as an electrode pad. However,
In order to improve the adhesiveness when connecting the semiconductor substrate 1 to a printed circuit board, an alumina substrate or the like via this electrode pad, generally, an electroless plating process is further performed, as shown in FIG.
As shown in (c), a metal such as nickel or copper is deposited on the surface of the zinc replacement portion 5 to form the electrode pad 6. During the zinc replacement treatment and the electroless plating on the surface of the zinc replacement part 5, the zinc replacement part 5 has an equipotential, so that the metal is uniformly deposited, and the electrode pad 6 has a uniform film thickness and film quality.
Is formed. After that, in order to electrically insulate each electrode pad 6, the lead wire 7 connected to the common conductor wire 8 provided in the peripheral portion of the semiconductor circuit is cut from above the insulating layer 3.

【００１７】（実施例２）図２（ａ）乃至（ｆ）を用い
て、本発明にかかる他の電極パッドの形成方法について
説明する。なお、従来の形成方法と同様の方法について
は説明を簡略化し、同じ構成部分については同じ番号を
使用する。(Embodiment 2) Another method of forming an electrode pad according to the present invention will be described with reference to FIGS. 2 (a) to 2 (f). The description of the same method as the conventional forming method will be simplified, and the same numbers will be used for the same components.

【００１８】従来の形成方法と同様に、図２（ａ）のよ
うに、半導体基板１には各種回路素子Ｅが形成され、ま
た半導体基板１の表面には各種回路素子Ｅを相互に接続
するための配線部２が形成される。さらに、窒化シリコ
ン膜あるいは酸化シリコン膜等からなる絶縁層３が形成
される。そして、開口部４を設けて、配線部２の所定位
置のアルミニウム表面を露出させる。Similar to the conventional forming method, as shown in FIG. 2A, various circuit elements E are formed on the semiconductor substrate 1, and various circuit elements E are connected to each other on the surface of the semiconductor substrate 1. The wiring part 2 for forming is formed. Further, the insulating layer 3 made of a silicon nitride film or a silicon oxide film is formed. Then, the opening 4 is provided to expose the aluminum surface at a predetermined position of the wiring part 2.

【００１９】次に、蒸着等の手段を用いて、図２（ｂ）
のように、絶縁層３の上から、例えばチタン層９およ
び、例えば銅層１０からなる金属層を順番に、積層状に
成膜する。後述する無電解メッキによってニッケルを析
出させる際に、銅層１０を下地として設けておくと、ニ
ッケルを容易に析出させることができる。また、アルミ
ニウムの配線部２と銅層１０との間にチタン層９を設け
ると、配線部２と銅層１０の密着強度を高めることがで
きる。これらの、金属層を設けたことにより、開口部４
によって露出した配線部２のアルミニウム表面は短絡さ
れて同電位となる。なお、本実施例のようにチタン層９
および銅層１０の２層からなる金属層とせずに、他の組
み合わせ、あるいは３層以上又は１層の金属層であって
も良い。Next, as shown in FIG. 2B, a means such as vapor deposition is used.
As described above, a metal layer made of, for example, a titanium layer 9 and a copper layer 10, for example, is sequentially formed in a laminated form on the insulating layer 3. When nickel is deposited by electroless plating, which will be described later, if the copper layer 10 is provided as a base, nickel can be easily deposited. Further, when the titanium layer 9 is provided between the aluminum wiring portion 2 and the copper layer 10, the adhesion strength between the wiring portion 2 and the copper layer 10 can be increased. By providing these metal layers, the openings 4
The aluminum surface of the exposed wiring portion 2 is short-circuited to have the same potential. In addition, as in the present embodiment, the titanium layer 9
Instead of the two metal layers of the copper layer 10, other combinations, or three or more metal layers or one metal layer may be used.

【００２０】さらに、フォトリソグラフィ技術を用い
て、図２（ｃ）のように、所定形状のレジストマスク１
１を形成する。レジストマスク１１には、絶縁層３に形
成された開口部４の上方に開口部１２が形成される。そ
して、銅層１０の表面部分を露出させる。Further, using a photolithography technique, as shown in FIG. 2C, a resist mask 1 having a predetermined shape is formed.
1 is formed. An opening 12 is formed in the resist mask 11 above the opening 4 formed in the insulating layer 3. Then, the surface portion of the copper layer 10 is exposed.

【００２１】この後、図２（ｄ）のように、例えば無電
解メッキを施して、開口部１２によって露出した銅層１
０の表面部分に、例えばニッケル、銅等の金属層１３を
形成する。さらに、この金属層１３の表面には、金属層
１３の表面の酸化を防止するため、例えば酸化防止金
属、例えば金を用いて金メッキ層１４を形成する。な
お、金メッキ層１４は形成しなくても良い。Thereafter, as shown in FIG. 2D, for example, electroless plating is performed to expose the copper layer 1 exposed through the opening 12.
A metal layer 13 of nickel, copper, or the like is formed on the surface portion of 0. Further, on the surface of the metal layer 13, in order to prevent the surface of the metal layer 13 from being oxidized, a gold plating layer 14 is formed using, for example, an anti-oxidation metal such as gold. The gold plating layer 14 may not be formed.

【００２２】次に、図２（ｅ）のように、レジストマス
ク１１を除去して、ニッケル層１３および金メッキ層１
４を形成した部分以外の銅層１０の表面部分を露出させ
る。この後、金メッキ層１４をエッチングマスクとして
使用して、銅層１０と熱硫酸等を反応させ、金メッキ層
１４を形成した部分以外の銅層１０を除去する。さらに
引続き、チタン層９と熱硫酸等を反応させ、金メッキ層
１４が形成された下部のチタン層９以外の部分を除去す
る。このような形成方法により、半導体基板１の表面に
形成された配線部２の所定位置表面には、図２（ｆ）の
ように、電極パッド１５が形成される。なお、本実施例
ではエッチングに際して、金メッキ層１４をエッチング
マスクとして使用したが、金メッキ層１４を形成しない
場合にはフォトレジスト膜等を用いてエッチングしても
良い。この電極パッド１５の形成方法においては、亜鉛
置換（ジンケ−ト）処理を行なわないので、開口部４に
よって露出した配線部２のアルミニウム部分の厚みが薄
くなり、この部分の抵抗値が高くなるという欠点が生じ
ない。Next, as shown in FIG. 2E, the resist mask 11 is removed, and the nickel layer 13 and the gold plating layer 1 are removed.
The surface portion of the copper layer 10 other than the portion where 4 is formed is exposed. Then, using the gold plating layer 14 as an etching mask, the copper layer 10 is reacted with hot sulfuric acid or the like to remove the copper layer 10 other than the portion where the gold plating layer 14 is formed. Further, subsequently, the titanium layer 9 is reacted with hot sulfuric acid or the like to remove the portion other than the lower titanium layer 9 where the gold plating layer 14 is formed. By such a forming method, the electrode pad 15 is formed on the surface of the wiring portion 2 formed on the surface of the semiconductor substrate 1 at a predetermined position as shown in FIG. In the present embodiment, the gold plating layer 14 was used as an etching mask during etching, but if the gold plating layer 14 is not formed, etching may be performed using a photoresist film or the like. In this method of forming the electrode pad 15, since the zinc substitution (zincate) treatment is not performed, the thickness of the aluminum portion of the wiring portion 2 exposed by the opening 4 becomes thin and the resistance value of this portion becomes high. There are no drawbacks.

【００２３】[0023]

【発明の効果】本発明の、半田バンプを形成するために
使用する電極パッドは上述のように形成されるため、膜
厚および膜質が均一な電極パッドが形成でき、この結
果、電気的および機械的信頼性が高まる。また、製品歩
留まりが高くなるため、安価に製造できる。Since the electrode pads used for forming the solder bumps of the present invention are formed as described above, it is possible to form electrode pads having a uniform film thickness and film quality, which results in electrical and mechanical properties. Reliability increases. Further, since the product yield is high, it can be manufactured at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係る、電極パッドの形成方法の概略図
である。FIG. 1 is a schematic view of a method of forming an electrode pad according to the present invention.

【図２】本発明に係る、配線部としてアルミニウムを使
用した場合の、他の電極パッドの形成方法の概略図であ
る。FIG. 2 is a schematic view of another electrode pad forming method according to the present invention when aluminum is used as the wiring portion.

【図３】従来の、電極パッドの形成方法の概略図であ
る。FIG. 3 is a schematic view of a conventional electrode pad forming method.

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ 配線部 ３ 絶縁層 ４ 開口部 ５ 亜鉛置換部 ６ 電極パッド ７ リ−ド線 ８ 共通導線 ９ チタン層 １０ 銅層 １１ レジストマスク １２ 開口部 １３ 金属層 １４ 金メッキ層 １５ 電極パッド Ｅ 回路素子 1 Semiconductor Substrate 2 Wiring Part 3 Insulating Layer 4 Opening 5 Zinc Substitution 6 Electrode Pad 7 Lead Wire 8 Common Conductive Wire 9 Titanium Layer 10 Copper Layer 11 Resist Mask 12 Opening 13 Metal Layer 14 Gold Plating Layer 15 Electrode Pad E Circuit element

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板の表面に複数の配線部を形
成する工程と、前記配線部の一部分を導体部を介して相
互に短絡して等電位にする工程と、前記配線部の所定部
分に無電解メッキによって電極パッドを形成する工程
と、前記導体部の少なくとも一部分を除いて電極パッド
を相互に絶縁する工程とからなる電極パッドの形成方
法。1. A step of forming a plurality of wiring portions on a surface of a semiconductor substrate, a step of short-circuiting a part of the wiring portions to each other via a conductor portion to make them equipotential, and a predetermined portion of the wiring portion. A method of forming an electrode pad, comprising: a step of forming an electrode pad by electroless plating; and a step of insulating the electrode pad from each other except at least a part of the conductor portion. 【請求項２】 半導体基板の表面に配線部と、該配線
部の所定部分から引き出されるリ−ド線と、該リ−ド線
に接続された共通導線を形成する工程と、前記配線部の
所定部分を露出する開口部を有した絶縁層を形成する工
程と、前記開口部によって露出した前記配線部の所定部
分に無電解メッキによって金属を析出させる工程と、前
記リ−ド線を切断する工程とからなる電極パッドの形成
方法。2. A step of forming a wiring portion on a surface of a semiconductor substrate, a lead wire extending from a predetermined portion of the wiring portion, and a common conductor wire connected to the lead wire, and a step of forming the wiring portion. Forming an insulating layer having an opening exposing a predetermined portion; depositing a metal on the predetermined portion of the wiring portion exposed by the opening by electroless plating; cutting the lead wire A method of forming an electrode pad, which comprises the steps of: 【請求項３】 半導体基板の表面に配線部を形成する
工程と、前記配線部の所定部分を露出する複数の開口部
を有した絶縁層を形成する工程と、前記絶縁層の表面
に、前記開口部間の露出した配線部を短絡する金属層を
形成する工程と、前記開口部を埋める前記金属層の表面
部分を露出する開口部を有するレジストマスクを形成す
る工程と、該レジストマスクの開口部によって露出した
前記金属層の表面に金属を析出させる工程と、前記レジ
ストマスクを除去するとともに、析出した金属部分以外
の金属層を除去する工程とからなる電極パッドの形成方
法。3. A step of forming a wiring portion on a surface of a semiconductor substrate, a step of forming an insulating layer having a plurality of openings exposing a predetermined portion of the wiring portion, and a step of forming an insulating layer on the surface of the insulating layer. Forming a metal layer that short-circuits exposed wiring between the openings; forming a resist mask having an opening that exposes a surface portion of the metal layer that fills the opening; and opening the resist mask. A method of forming an electrode pad, comprising: a step of depositing a metal on the surface of the metal layer exposed by a portion; and a step of removing the resist mask and removing a metal layer other than the deposited metal portion.
JP2180695A 1995-02-09 1995-02-09 Method for forming electrode pad Expired - Lifetime JP3702480B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2180695A JP3702480B2 (en) 1995-02-09 1995-02-09 Method for forming electrode pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2180695A JP3702480B2 (en) 1995-02-09 1995-02-09 Method for forming electrode pad

Publications (2)

Publication Number Publication Date
JPH08222626A true JPH08222626A (en) 1996-08-30
JP3702480B2 JP3702480B2 (en) 2005-10-05

Family

ID=12065304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2180695A Expired - Lifetime JP3702480B2 (en) 1995-02-09 1995-02-09 Method for forming electrode pad

Country Status (1)

Country Link
JP (1) JP3702480B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007306027A (en) * 2007-07-23 2007-11-22 Ibiden Co Ltd Semiconductor chip
JP2017005100A (en) * 2015-06-10 2017-01-05 三菱電機株式会社 Semiconductor chip, semiconductor device, and method of manufacturing them

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007306027A (en) * 2007-07-23 2007-11-22 Ibiden Co Ltd Semiconductor chip
JP4679553B2 (en) * 2007-07-23 2011-04-27 イビデン株式会社 Semiconductor chip
JP2017005100A (en) * 2015-06-10 2017-01-05 三菱電機株式会社 Semiconductor chip, semiconductor device, and method of manufacturing them

Also Published As

Publication number Publication date
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