JPS58201121A - Correcting system of delay time - Google Patents
Correcting system of delay timeInfo
- Publication number
- JPS58201121A JPS58201121A JP57083024A JP8302482A JPS58201121A JP S58201121 A JPS58201121 A JP S58201121A JP 57083024 A JP57083024 A JP 57083024A JP 8302482 A JP8302482 A JP 8302482A JP S58201121 A JPS58201121 A JP S58201121A
- Authority
- JP
- Japan
- Prior art keywords
- correction
- circuit
- time
- delay
- point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Pulse Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
発明の対象
本発明は、試験機や、計算機などで、クロック発生器か
ら、クロックを使用する所までの遅。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a test machine, a computer, etc., in which the clock is slow from the clock generator to the point where the clock is used.
延時間を同一にする為の遅延時間補正方式に関する。This invention relates to a delay time correction method for making extension times the same.
従来技術
試験機の駆動回路における従来のクロック間タイミング
スキーー自動補正回路を第1図によ。FIG. 1 shows a conventional clock-to-clock timing key automatic correction circuit in the drive circuit of a conventional test machine.
り説明する。I will explain.
本回路は、基準駆動回路1,6点からf点までの遅延時
間iafと、!1点からf点までの遅延。This circuit has a delay time iaf from the reference drive circuit points 1 and 6 to point f, and! Delay from point 1 to point f.
時間tyfを、同一にする為の遅延回路2と、被測定駆
動回路3の出力を比較器4に接続する為のS F(11
5、S F(2+ 6及び、比較器4の出力により制御
される遅延回路7より構成される。A delay circuit 2 for making the time tyf the same, and an SF (11
5, S F (2+6) and a delay circuit 7 controlled by the output of the comparator 4.
タイミングスキュー補正は、第1VcSW(2)6を2
点に接続し、基準。駆動回j18iの出力を、比較器4
づ検出できる条件で、SIF’(1)5をC点に。Timing skew correction is performed by setting the first VcSW (2) 6 to 2.
Connect points and standards. The output of the drive circuit j18i is sent to the comparator 4
Set SIF'(1)5 to point C under conditions that allow detection.
S F (216をd点に接続し、駆動回路乙の出力が
。S F (Connect 216 to point d, and the output of drive circuit B.
比較器4で検出できる様に、遅延回路7を調整する。The delay circuit 7 is adjusted so that the comparator 4 can detect the signal.
この時、遅延回路7の遅延時間を最小遅延時間から5順
次遅延時間を大きくして行き、比較。At this time, the delay time of the delay circuit 7 is increased in five sequential order from the minimum delay time and compared.
器4が駆動回路6の出力を検出した時点で、遅。When the device 4 detects the output of the drive circuit 6, it is too late.
延時間を大きくするのを停止する。Stop increasing the extension time.
または、遅延回路7の遅延時間を最大遅延時。Or, the delay time of delay circuit 7 is the maximum delay.
間から、順次遅延時間を小さくして行き、比較。Start by decreasing the delay time and compare.
器4が、駆動回路乙の出力を検出I7た時点で、4遅延
時間を小さくするのを停止する。When the device 4 detects the output of the drive circuit B, it stops reducing the delay time.
第2に、他の駆動回路についても1選択回路48により
選択して1選択した駆動回1i!8Vc接続さ。Second, the other drive circuits are also selected by the 1 selection circuit 48, and the 1 selected drive circuit 1i! 8Vc connection.
れる遅延回路の調整を同様に行う。 ]1゜こ
の動作を、すべての補正対象について行うことにより、
基準駆動回路の遅延時間に、すべての補正対象、駆動回
路の遅延時間を合わすことが可能となる。Similarly, adjust the delay circuit. ]1゜By performing this operation for all correction targets,
It becomes possible to match the delay times of all correction targets and drive circuits to the delay time of the reference drive circuit.
しかし、この方式では、!I点から1点までの遅延時間
と、補正対象である駆動回路乙の出力α点から、比較器
40入力f点までの遅延時間及び、他のすべての補正対
象の同じ所の、遅延時間差は、補正後のタイミングスキ
ューの許容差と比較して、充分小さい必要がある。But with this method! The delay time difference between the delay time from point I to point 1, the delay time from the output α point of drive circuit B, which is the correction target, to the comparator 40 input point F, and the delay time difference at the same point for all other correction targets is , must be sufficiently small compared to the timing skew tolerance after correction.
このため、補正対象が多くなると、試験機の。For this reason, when the number of correction targets increases, the number of correction targets increases.
製造が困難になる。Manufacturing becomes difficult.
また、遅延回路への遅延時間設定回数が多い。Also, the number of times the delay time is set in the delay circuit is large.
為、補正時間が長くなる。Therefore, the correction time becomes longer.
発明の目的 本発明の目的とするところは、従来技術での。Purpose of invention The object of the present invention is to overcome the prior art.
問題点を除去するものであり、補正に使用する回路など
の、遅延時間差及び、補正対象のタイミングスキューを
測定し、補正することを可能にすることにより、試験機
や計算機の製造を容易にする遅延時間補正方式を提供す
ることにある。This eliminates problems and makes it easier to manufacture test machines and calculators by making it possible to measure and correct delay time differences and timing skews to be corrected, such as in circuits used for correction. An object of the present invention is to provide a delay time correction method.
本発明の特徴とするところは、″4Il補正クロッ。The feature of the present invention is "4Il correction clock."
り及び、補正を行う為の測定系遅延時間を測定し、測定
した時間力、1ら、クロックスキューを求め、遅延回路
に、遅延時間を設定することである。In addition, the measurement system delay time for performing correction is measured, the measured time force, 1, and clock skew are determined, and the delay time is set in the delay circuit.
発明の実施例
本発明の一実施例である試験機の遅延時間設定回数を第
2図により説明する。Embodiment of the Invention The number of delay time settings of a testing machine which is an embodiment of the present invention will be explained with reference to FIG.
本回路は、6点とd点の時間差を測定する時。This circuit measures the time difference between point 6 and point d.
開蓋測定回路1.測定結果から、補正値を求め、。Open lid measurement circuit 1. Calculate the correction value from the measurement results.
遅延回路5の制御を行う制御部2と、駆動回路、4の出
力を時間差測定回路1に接続するための3゜SW (I
j 5 、選択回路6及びb点d点間の遅延時間測定に
使用するS W (217より構成される。 。A 3° SW (I
j 5 , the selection circuit 6 and the SW used for measuring the delay time between point b and point d (composed of 217).
タイミングスキニーの補正は、第1に、5F(i15を
0点に接続し、6点は開・放端とし、、5F(2)7を
閉じ時間差測定回路1の入力であるd点と6点を短絡し
、第3図に示す波形がd、を点の入力となる様にする。To correct timing skinny, first, connect 5F (i15 to point 0, leave point 6 open/open, and close 5F (2) 7 to connect point d, which is the input of time difference measurement circuit 1, and point 6. are short-circuited so that the waveform shown in FIG. 3 becomes the input point d.
第2に時間差測定回路1の比較電圧を6点は。Second, compare the voltages of the time difference measuring circuit 1 at 6 points.
VRl、 d 点ハVR2に設定することにより%de
点から6点までの測定系の往復の遅延時間tsが測定で
きる。By setting VRl, d point to VR2, %de
The round trip delay time ts of the measurement system from point to point 6 can be measured.
この測定遅延時間t・は1選択回路6を切換iて丁べて
の補正対象の糸について測定する。This measurement delay time t. is measured for each yarn to be corrected by switching the 1 selection circuit 6.
第31C,5W(1)5を6点に接続シ、5W(2)7
゛を開き6点に対するd点の時間差tgdを測定等る。No. 31C, 5W (1) 5 connected to 6 points, 5W (2) 7
The time difference tgd of point d with respect to the six points is measured.
の関係があるため txを求める。Because there is a relationship between Find tx.
このtxをすべての補正対象につめて求める。This tx is calculated for all correction targets.
第4に、第3で求めたすべてのtxが同一になる様に、
各遅延回路3に設定する値を求め設定する。Fourthly, so that all tx obtained in the third step are the same,
A value to be set in each delay circuit 3 is determined and set.
実施例では、補正対象の遅延時間を測定する測定系の遅
延時間を測定し、計算により補正を行うため、補正対象
が多くても1等長配線なiを行う必要がなく、製造が困
難とはならず、ま゛た。補正対象の遅延時間も測定し、
計算により“補正を行うので、遅延回路への設定も一度
で門い。In the example, the delay time of the measurement system that measures the delay time of the correction target is measured and the correction is performed by calculation, so even if there are many correction targets, it is not necessary to perform wiring of equal length i, which makes manufacturing difficult. It didn't happen, it didn't. Also measure the delay time to be corrected,
Since the correction is performed by calculation, the settings for the delay circuit can be set in one go.
発明の効果 本発明によれば、遅延時間を測定するため、。Effect of the invention According to the invention, to measure the delay time.
計算により、補正値を求めることが可能となり、。By calculation, it is possible to find the correction value.
製造上の問題を少くできる。Reduces manufacturing problems.
又、補正が一度の測定と、遅延回路への設定で良いため
、補正時間の短縮も可能である。 。Furthermore, since correction only requires one measurement and setting to a delay circuit, it is possible to shorten the correction time. .
第1図は、従来技術による試験機駆動回路の。
タイミングスキー−自動補正回路図、第2図は本発明の
一実施例の試験機駆動回路のタイミングスキュー自動補
正回路図、第3図は同じ゛(測定系の測定時の波形図で
ある。
1・・・時間差測定器。
2・・・制御部。
6・・・遅延回路。
7 ・
27 図
才 2 図
才 3 図
−一−チ吟圏FIG. 1 shows a test machine drive circuit according to the prior art. Timing ski - automatic correction circuit diagram. Fig. 2 is a timing skew automatic correction circuit diagram of a test machine drive circuit according to an embodiment of the present invention. Fig. 3 is the same waveform diagram during measurement of the measurement system. 1 ...Time difference measuring device. 2.. Control unit. 6. Delay circuit. 7. 27 Figure 2 Figure 3 Figure 1
Claims (1)
すべきクロックとの時間差を測定し、切。 換回路の電気長をあらかじめ測定しておき、前記基準ク
ロックとの時間差に補正を行い、この補正後の時間差が
なくなる様に前記プログラマブル遅延回路を制御し、ク
ロック位相差をなくし調整を完了させ、さらに切換回路
により次のクロックを前記と同様にして調整していき、
装置内の全てのクロックの位相差をなくすることを特徴
とする遅延時間補正方式。[Claims] 1. Supplying multiple clocks to multiple points. in each clock distribution path in equipment that requires with a programmable delay circuit and said clock supply. It has a switching circuit from supply pressure to time difference measuring device. Measure the time difference between the reference clock and the clock to be adjusted via the switching circuit using the measuring device, and then turn it off. measuring the electrical length of the switching circuit in advance, correcting the time difference with the reference clock, controlling the programmable delay circuit so that the time difference after this correction is eliminated, and completing the adjustment by eliminating the clock phase difference; Furthermore, the next clock is adjusted by the switching circuit in the same way as above,
A delay time correction method characterized by eliminating phase differences between all clocks within the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57083024A JPS58201121A (en) | 1982-05-19 | 1982-05-19 | Correcting system of delay time |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57083024A JPS58201121A (en) | 1982-05-19 | 1982-05-19 | Correcting system of delay time |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58201121A true JPS58201121A (en) | 1983-11-22 |
JPH034925B2 JPH034925B2 (en) | 1991-01-24 |
Family
ID=13790664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57083024A Granted JPS58201121A (en) | 1982-05-19 | 1982-05-19 | Correcting system of delay time |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58201121A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01216274A (en) * | 1988-02-25 | 1989-08-30 | Fujitsu Ltd | Lsi testing equipment |
US6784684B2 (en) | 2001-09-25 | 2004-08-31 | Renesas Technology Corp. | Testing apparatus including testing board having wirings connected to common point and method of testing semiconductor device by composing signals |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS524751A (en) * | 1975-06-27 | 1977-01-14 | Ibm | Automatic clock control system |
JPS55960A (en) * | 1978-06-20 | 1980-01-07 | Fujitsu Ltd | Clock distributor |
-
1982
- 1982-05-19 JP JP57083024A patent/JPS58201121A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS524751A (en) * | 1975-06-27 | 1977-01-14 | Ibm | Automatic clock control system |
JPS55960A (en) * | 1978-06-20 | 1980-01-07 | Fujitsu Ltd | Clock distributor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01216274A (en) * | 1988-02-25 | 1989-08-30 | Fujitsu Ltd | Lsi testing equipment |
US6784684B2 (en) | 2001-09-25 | 2004-08-31 | Renesas Technology Corp. | Testing apparatus including testing board having wirings connected to common point and method of testing semiconductor device by composing signals |
Also Published As
Publication number | Publication date |
---|---|
JPH034925B2 (en) | 1991-01-24 |
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