JPS58199526A - Method and apparatus for forming pattern - Google Patents
Method and apparatus for forming patternInfo
- Publication number
- JPS58199526A JPS58199526A JP8144782A JP8144782A JPS58199526A JP S58199526 A JPS58199526 A JP S58199526A JP 8144782 A JP8144782 A JP 8144782A JP 8144782 A JP8144782 A JP 8144782A JP S58199526 A JPS58199526 A JP S58199526A
- Authority
- JP
- Japan
- Prior art keywords
- data
- pattern
- patterns
- memory
- types
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 8
- 230000015654 memory Effects 0.000 claims abstract description 26
- 230000002194 synthesizing effect Effects 0.000 claims abstract description 6
- 238000010894 electron beam technology Methods 0.000 claims abstract description 5
- 230000006870 function Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000609 electron-beam lithography Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はパターン作成方法および装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern creation method and apparatus.
従来、電子線描画装置において、１つのマスク上に複数
種のパターン全描画する場合、電子線描自装重用パター
ンデータの作成または変換の段階でコンピュータを周込
たプログラム処理にようそれぞれのパターンのデータ１
ｆｅａんで別のデータ奮作って込る。Conventionally, in an electron beam lithography system, when multiple types of patterns are all drawn on one mask, each pattern's data is processed by a computer program at the stage of creating or converting pattern data for the electron beam lithography system. 1
I worked hard to create other data using fea.
ところが、このような従来技術では、データの合成のた
めに多量のメモリ領域が必要であり、処理に時間かかか
ると込う問題がある。また、データの合成罠より、デー
タファイルの増加、データ容置の増加の必要性が生じて
し１う。However, such conventional techniques require a large amount of memory area for data synthesis, and have problems in that processing takes a long time. Furthermore, due to the data synthesis trap, it becomes necessary to increase the number of data files and data storage.
さらに、従来の電子線描画装置でに、１つの品種のパタ
ーン１ｔＶするチップ毎にマスクへの１回の描画全打込
、その後に別の品種のパターン紫有するチップにつ込て
マスクへの描Ｔｈｋ行ってＬｎルので、たとえば３品棟
の異なるパターンｋｍつ場合にｒＸ３回の描画操作音１
つのマスクに対して別々に行う必要かあり、描画時間が
約３倍になってしまうことになる。その結果、単−品種
のものに比べて描＋［７１１時間が長く、装置の利用動
量か悪くなるという問題かある。Furthermore, with a conventional electron beam lithography system, one full writing process is performed on a mask for each chip with a pattern of 1 tV of one type, and then the writing is performed on a mask for each chip with a purple pattern of a different type. Thk and Ln le, so for example, if there are 3 different patterns of 3 products, rX 3 drawing operation sounds 1
It is necessary to perform this process separately for each mask, which means that the drawing time will be approximately tripled. As a result, there is a problem that the drawing time is longer than that of a single type, and the amount of equipment utilization is reduced.
本発明の目的に、前記従来技術の欠点全解消し、短時間
の描画時間で効率的な複数種パターンの描画を行うこと
のできるパターン作成方法および装置を提供することに
るる。SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern forming method and apparatus which can eliminate all of the drawbacks of the prior art and can efficiently draw a plurality of types of patterns in a short drawing time.
この目的を達成するため、本発明のパターン作成方法は
、電子＆’ｉ？用いて１つのマスク上に複数種のパター
ンを描画するに際して、複数種のパターンのデータを合
成しながら、パターンを描画すること全特徴とするもの
である。また、本発明のパターン作成装置Ｉは、複数種
のパターンデータ會合成するため、描画時にパターンデ
ータ會一時的に記憶するパターンメモリに、複数種のデ
ータ全合成する論理和機能を付加したこと全特徴とする
ものである。To achieve this objective, the pattern making method of the present invention uses electronic &'i? When drawing a plurality of types of patterns on one mask using a mask, the entire feature is that the pattern is drawn while synthesizing data of the plurality of patterns. Further, in order to synthesize a plurality of types of pattern data, the pattern creation device I of the present invention has a logical OR function for completely synthesizing the plurality of types of data to the pattern memory that temporarily stores the pattern data at the time of drawing. This is a characteristic feature.
以下、不発＠８を図面に示す実施例にしたがって詳細に
説明する。Hereinafter, misfire@8 will be explained in detail according to an embodiment shown in the drawings.
第１図に本発明によるパターン作成装置の一央！ｌ［Ｉ
ｉ ｆｉｌ ’に示すブロック図である。FIG. 1 shows the central part of the pattern making apparatus according to the present invention. l[I
It is a block diagram shown in ifil'.
本実施例において、ｌは複数種の異なるパターンのデー
タＩＡ、ＩＢ、ｌｏ會有するパターンデータでめ夛、こ
れらの複数種のデータＩＡ、ＩＢ。In this embodiment, l is pattern data having a plurality of different patterns of data IA, IB, lo, and these plural types of data IA, IB.
１０は中央処理装置（ｏｐｔｙ）２に取ｐ込まれる。10 is taken into the central processing unit (opty) 2.
０ＰＵ２はＯＲゲート３とデコーダ４′にブトしてパタ
ーンメモリ５に接続式れ、このＯＲゲート３はパターン
メモリ５のリセット回路に設けられ、指示により、メモ
リのリセットは行わないで、リセット完了信号１ｉ−Ｏ
ＰＵＩＣ戻丁機１１に来π丁。0PU2 is connected to the pattern memory 5 through an OR gate 3 and a decoder 4', and this OR gate 3 is provided in the reset circuit of the pattern memory 5, and upon instruction, the reset completion signal is output without resetting the memory. 1i-O
I came to PUIC return machine 11.
デコーダ４はパターンメモリ５の分割メモリにそれぞれ
独立のデータＬＡ、ＩＢ、１０會同時にまたは連続して
入力するための分割メモリ間のデコーダとしての役割を
果たすものである。The decoder 4 serves as a decoder between the divided memories for inputting 10 independent data LA, IB, and 10 data to the divided memories of the pattern memory 5 simultaneously or successively.
パターンメモリ５はパターンデータ１１−一時的に配憧
するものであｐ１複数橿のデータＩＡ。The pattern memory 5 has pattern data 11 - data IA for temporary attachment p1.
ＩＢ、１０に応じて任意のアドレスで分割された独立的
なメモリ領域５Ａ％ ５Ｂ％ ５０ｋＮしている。It has an independent memory area of 5A% 5B% 50kN divided at arbitrary addresses according to IB, 10.
前記パターンメモリ５は、その分割メモリを単一メモリ
として合成出力するためデータ出力回路に設けたゲート
回路６に接続されている。このゲート回路６はＯＲゲー
ト７を介して電子線オン−オフ制御回路８に接続されて
いる。ＯＲゲート７はパターンメモリ５のデータ出方回
路におりて、指示により、出力は行わずに、出力完了信
号音０ＰＵ２に戻す機能を備えている。The pattern memory 5 is connected to a gate circuit 6 provided in the data output circuit for outputting the divided memories as a single memory. This gate circuit 6 is connected to an electron beam on/off control circuit 8 via an OR gate 7. The OR gate 7 is located in the data output circuit of the pattern memory 5, and has a function of returning to the output completion signal sound 0PU2 without outputting according to an instruction.
本実施例の作用につｂて説明すると、本実施例では、描
画時にパターンデータ１′ｔ−変換して電子線ノオンー
オフ高速制御に適合したオン−オフのビット信号がパタ
ーンメモリ５に配憶され、また該パターンメモリ５が複
数種のデータＩＡ、ＩＢ。To explain the operation of this embodiment, in this embodiment, the pattern data 1't-converts during drawing and on-off bit signals suitable for high-speed electron beam on-off control are stored in the pattern memory 5. , and the pattern memory 5 contains a plurality of types of data IA, IB.
１０ｉ合成するための論理和機能を備えて粘るので、描
画時には、複数棟の異なるデータＩＡ。Since it is equipped with a logical sum function for 10i compositing, different data IA of multiple buildings can be used when drawing.
ＩＢ、１０會合成しながらｌｌｇＩの描画操作で全パタ
ーンを各チップの順序通りに描画して行くことができる
。While IB and 10 are combined, all patterns can be drawn in the order of each chip using the drawing operation of llgI.
すなわち、本実施例では、パターンメモリ５に論理和機
能か付加されてｂることにより、複数の異なるデータＩ
Ａ％ １１％ １０に該パターンメモリ５に人力す
れば、これらのデータＩＡ％ＩＢ。That is, in this embodiment, by adding a logical OR function to the pattern memory 5, a plurality of different data I
If A% 11% 10 is manually input to the pattern memory 5, these data IA%IB.
１０１を合成した合成データが自動的に得られ、この合
成データに基づいて電子−オン−オフ制御回路８を制御
しながら電子憩描画七行うことにより、複数種混載マス
クでも１回の描１ｆ１ｉ操作で単一品種と同程度の高速
描画が可能となる。101 is automatically obtained, and electronic diverter drawing is performed while controlling the electronic on-off control circuit 8 based on this synthetic data, one drawing 1f1i operation can be performed even with multiple types of mixed masks. This enables high-speed drawing comparable to that of a single type.
第２図は本発明によるパターン作成装置の他の１つの実
施例上水すブロック図である。FIG. 2 is a block diagram of another embodiment of the pattern forming apparatus according to the present invention.
本実施例では、パターンメモリ５が単一メモリであり、
デコーダ４とゲート回路６か省略されているか、前記実
施例と同様に複数種のデータＩＡ。In this embodiment, the pattern memory 5 is a single memory,
The decoder 4 and the gate circuit 6 are omitted, and a plurality of types of data IA are provided as in the previous embodiment.
ＩＢ、１０會自動的に合成して高速描画上行うことがで
きる。IB, 10 can be automatically synthesized for high-speed drawing.
なお、本発明にお込ては、同じパターンメモリでデータ
にオフセラ）ｔ−加えてデータを合成しながらパターン
を描画することも可能である。In addition, in the present invention, it is also possible to draw a pattern while adding offset data to data using the same pattern memory and composing the data.
以上説明したように、本発明によれば、１つのマスク上
に複数種のパターンを描画する場合でも短時間で効率的
な高速描画が可能であり、装置のオ０用効率七向上させ
ることができる。As explained above, according to the present invention, even when drawing multiple types of patterns on one mask, efficient high-speed drawing is possible in a short time, and the efficiency of the apparatus can be improved. can.
第１図に本発明によるパターン作成装置の−実施し１：
全示すブロック図、
第２図は本発明の他の１つの実施例上水すブロック図で
ある。
１・・・パターンデータ、ＩＡ、ＩＢ、１０・・・デー
タ、２・・・中央処理装置（ＯＰＵ）、３・・・ＯＲゲ
ート、４・・・デコーダ、５・・・パターンメモリ、５
Ａ、 ５Ｂ。
５０・・・メモリ領域、６・・・ゲート回路、７・・・
ＯＲゲート、８・・・電子線オン−オフ制御回路。
第 １ 図
第 ２ 図FIG. 1 shows a first implementation of the pattern making apparatus according to the present invention:
Complete Block Diagram FIG. 2 is a block diagram of another embodiment of the present invention. 1... Pattern data, IA, IB, 10... Data, 2... Central processing unit (OPU), 3... OR gate, 4... Decoder, 5... Pattern memory, 5
A, 5B. 50...Memory area, 6...Gate circuit, 7...
OR gate, 8...Electron beam on-off control circuit. Figure 1 Figure 2
Claims (1)
全描画するパターン作成方法において、複数種のパター
ンのデータ全合成しながらパターン全描画すること’に
％徴とするパターン作成方法。 ２、データの合成時にデータにオフセットｉ加えながら
合成を行うことに特徴とする特許請求の範囲第１項記載
のパターン作成方法。 ３、電子＃を用ｉて１つのマスク上に複数種のパターン
を描画するパターン作成装置において、複数線のパター
ンのデータ上域り込む中央処理装置と、複数種のデータ
全合成する論理和機軸を有し、描画時にパターンデータ
奮変換して電子巌のオンーオフ匍ｊ＃に適合した信号を
記憶するパターンメモリと全備えて−るパターン作成装
置。[Scope of Claims] 1. In a pattern creation method in which multiple types of patterns are all drawn on one mask including electron beams, there is a percentage characteristic of ``drawing all patterns while fully synthesizing data of multiple types of patterns''. How to create a pattern. 2. The pattern creation method according to claim 1, wherein the data is synthesized while adding an offset i to the data. 3. In a pattern creation device that draws multiple types of patterns on one mask using electron #, there is a central processing unit that enters the data of multiple line patterns, and an OR machine that completely synthesizes multiple types of data. and a pattern memory for converting pattern data at the time of drawing and storing a signal suitable for the on-off state of the electronic signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8144782A JPS58199526A (en) | 1982-05-17 | 1982-05-17 | Method and apparatus for forming pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8144782A JPS58199526A (en) | 1982-05-17 | 1982-05-17 | Method and apparatus for forming pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58199526A true JPS58199526A (en) | 1983-11-19 |
Family
ID=13746649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8144782A Pending JPS58199526A (en) | 1982-05-17 | 1982-05-17 | Method and apparatus for forming pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58199526A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6431418A (en) * | 1987-07-28 | 1989-02-01 | Toshiba Machine Co Ltd | Charged particle beam lithography equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4934777A (en) * | 1972-07-31 | 1974-03-30 | ||
| JPS545665A (en) * | 1977-06-15 | 1979-01-17 | Fujitsu Ltd | Electron beam exposure device |
| JPS56115535A (en) * | 1980-02-18 | 1981-09-10 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Electron beam exposure |
-
1982
- 1982-05-17 JP JP8144782A patent/JPS58199526A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4934777A (en) * | 1972-07-31 | 1974-03-30 | ||
| JPS545665A (en) * | 1977-06-15 | 1979-01-17 | Fujitsu Ltd | Electron beam exposure device |
| JPS56115535A (en) * | 1980-02-18 | 1981-09-10 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Electron beam exposure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6431418A (en) * | 1987-07-28 | 1989-02-01 | Toshiba Machine Co Ltd | Charged particle beam lithography equipment |
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