JPS58186958A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58186958A
JPS58186958A JP57069975A JP6997582A JPS58186958A JP S58186958 A JPS58186958 A JP S58186958A JP 57069975 A JP57069975 A JP 57069975A JP 6997582 A JP6997582 A JP 6997582A JP S58186958 A JPS58186958 A JP S58186958A
Authority
JP
Japan
Prior art keywords
resin
hole
semiconductor device
plate
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57069975A
Other languages
English (en)
Inventor
Fumio Sakurai
桜井 文雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57069975A priority Critical patent/JPS58186958A/ja
Publication of JPS58186958A publication Critical patent/JPS58186958A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は放熱板が外に露出し友樹脂封止型半導体装置に
関するものである。
一般に放熱板が外Kll出した樹脂封止型半導体装置に
おいて、単一の樹脂で封止した場合、ネジの締め付けや
落下等の111撃に対して半導体素子が欠ける等という
不具合が生じやすく高倍幀変の半導体装置を提供するた
めに困離があった。この対策のために従来は外装両市の
樹脂の池に半導体素子を梁軟なシリコン樹脂等を用いて
胤傾するようにコーティング等を行っている。しかし、
2種類の樹脂を用いるため熱膨張係数の違い等により熱
ストレスが生じ、ボンディングワイヤーを断線し友り、
また樹脂の密着強度が悪くなって耐湿性が弱くなる等と
いう欠陥が生じる。さらに、2種類の樹脂を使うので2
変作業を−ジ返さなければならず作業性も煩雑になる。
本発明の目的は単一の樹脂を用いて衝撃強度及び耐湿性
に非常に優れた半導体装置を提供するものである。
以下本発明の一実施例を図面により詳細に説明する。
第1図は従来の樹脂封止型半導体装置の内部構造図であ
る。放熱板lの上に半導体素子2を半田等により接着さ
せ、さらに外部リードとボンディングワイヤー3により
接続したものである。これを封市叫雪で覆って半導体装
置ができあがるが、このようKして作られた半導体装置
は放熱板lの外部に露出した部分で受ける外力がそのま
ま半導体票子2に伝わり、半導体素子2は封止樹脂で固
定されているため素子が割れたり、欠けたりするという
不具合が生じる。これを防ぐにはtIiに述べたように
柔軟なシリコン樹脂等で半導体素子2を覆うこと(図示
せず)Kより半導体素子2が受ける外力を吸収すること
ができる。しかし、この方法は前述したように作業の煩
雑さ中信頼度の問題等が生じる。
第2図に本発明の一実施例として、半導体装置の内部構
造図を示す、樹脂に封止されていると仁ろの放熱板10
の露出部側に細長い貫通孔15を設け、この貫通孔15
の長手方向の両側の放熱板残り部分16をできるだけ小
さく、放熱板1Gの板厚楊Wtにすることにする。さら
に仁の貫通孔15を樹脂封止時に封止樹脂17で完膚す
ることにより、放熱板lOの露出部で受けた外力を樹脂
内の貫通孔15で吸収してしまう丸め、半導体素子12
を単一の固い封止樹脂で覆っても1半導体素子12が割
れたり欠けたりするという仁とが防げる。しかも、樹脂
と放熱板との密着強変を着しく強くなる。これにより、
非常に作業性の良い高倍頼寂の半導体装置を提供するこ
とが可能となった。
【図面の簡単な説明】 第1図は従来の樹脂封止型半導体装置の内部構造図であ
る。第2図は本発明の樹脂封止型半導体装置の一実m例
の内部構造図である。 1−1O・・・・・・放熱板、2*12・・・・・・半
導体素子、3書13・・・・・・ボンディングワイヤー
、4s17・・・・・・樹脂封止部、15・・・・・・
長細い貫通孔、16・・・・・・板厚くらいの幅にする
場所 第1 図 第2図

Claims (1)

    【特許請求の範囲】
  1. 放熱板が樹脂の外Kll出した樹脂封止型半導体装置に
    おいて、樹脂で封止されているところの放熱板の露出部
    側に細長い貫通孔を設は九0とを特徴とする半導体装置
JP57069975A 1982-04-26 1982-04-26 半導体装置 Pending JPS58186958A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57069975A JPS58186958A (ja) 1982-04-26 1982-04-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57069975A JPS58186958A (ja) 1982-04-26 1982-04-26 半導体装置

Publications (1)

Publication Number Publication Date
JPS58186958A true JPS58186958A (ja) 1983-11-01

Family

ID=13418160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57069975A Pending JPS58186958A (ja) 1982-04-26 1982-04-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS58186958A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01147767U (ja) * 1988-03-28 1989-10-12
JPH01147766U (ja) * 1988-03-28 1989-10-12
JPH02129952A (ja) * 1988-11-09 1990-05-18 Fuji Electric Co Ltd 樹脂封止形半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01147767U (ja) * 1988-03-28 1989-10-12
JPH01147766U (ja) * 1988-03-28 1989-10-12
JPH02129952A (ja) * 1988-11-09 1990-05-18 Fuji Electric Co Ltd 樹脂封止形半導体装置の製造方法

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