JPS5817619A - Forming method for pattern - Google Patents
Forming method for patternInfo
- Publication number
- JPS5817619A JPS5817619A JP11578681A JP11578681A JPS5817619A JP S5817619 A JPS5817619 A JP S5817619A JP 11578681 A JP11578681 A JP 11578681A JP 11578681 A JP11578681 A JP 11578681A JP S5817619 A JPS5817619 A JP S5817619A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- electrode
- etched
- tapered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 18
- 239000010408 film Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 238000001020 plasma etching Methods 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 6
- 239000012298 atmosphere Substances 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WURBVZBTWMNKQT-UHFFFAOYSA-N 1-(4-chlorophenoxy)-3,3-dimethyl-1-(1,2,4-triazol-1-yl)butan-2-one Chemical compound C1=NC=NN1C(C(=O)C(C)(C)C)OC1=CC=C(Cl)C=C1 WURBVZBTWMNKQT-UHFFFAOYSA-N 0.000 description 1
- 229920000742 Cotton Polymers 0.000 description 1
- 241001474791 Proboscis Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011505 plaster Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は／９ターン形成方法に関し、特に半導体装置の
多層配線・９ターンの形成に適した方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming /9 turns, and particularly to a method suitable for forming multilayer interconnections and nine turns in semiconductor devices.
一般に、半導体装置の艇速においては、下地基板に種々
の段差が生じている九め、この段差上に配線ノ臂ターン
を形成する場合、前記段差が大きく、かつ急峻であると
、該配線・９ターンに段切れ不良を生じる。したがって
、半導体基板の段差部にテーノ量を付けることが望まれ
ている。Generally, at the speed of a semiconductor device, various steps are formed on the underlying substrate.When forming a wiring arm turn on the step, if the step is large and steep, the wiring A defective step occurs at turn 9. Therefore, it is desired to add a tenor amount to the stepped portion of the semiconductor substrate.
このようなことから、段差部にチー／ぐを付ける方法と
して、従来から湿式タイプの工、チング法を採用するこ
とが行なわれている。例えば、被エツチング膜の上層部
Ｉｌｃ該膜よシも工、チング速度の大きい材料膜を薄く
被着させ、この上にレジストノ！ターンを形成して湿式
１．チングすることによシテー・９状の段差を有する・
母ターンを形成する方法、或いはエツチング液中に界面
活性剤等管添加してレジスト／ＩＦターンと被工、テン
グ膜との密着性をテーパ状の段差を有するパターンを形
成する方法等がある。しかしながら、これら湿式１．チ
ング法はノ臂ターン精度等の点で問題があシ、これに代
って半導体装置に微細化に有効なドライエ、チング法が
主力になシつつある。ところが、かかるドライエ、チン
グ法ではテーパ状の段差を有するノナターンの形成が困
難となる。For this reason, wet-type machining, or the ching method, has traditionally been used as a method for attaching a tack to a stepped portion. For example, a thin film of a material with a high etching speed is applied to the upper layer Ilc of the film to be etched, and then a resist film is applied on top of the film. Form a turn and wet 1. It has a 9-shaped step by cutting.
There is a method of forming a master turn, or a method of adding a surfactant or the like to the etching solution to improve the adhesion between the resist/IF turn and the workpiece or proboscis film to form a pattern having a tapered step. However, these wet type 1. The chipping method has problems in terms of turning accuracy, etc., and in its place, the dryer and chipping method, which is effective for miniaturizing semiconductor devices, is becoming more and more popular. However, with such dry etching methods, it is difficult to form nonaturns having tapered steps.
即チ、等方性エツチングであるプラズマエツチングの場
合、第１図に示す如く基板１上に被覆され、マスク材（
例えばレゾストノ臂ターン）２から露出した被エツチン
グ膜は等方的にエツチングが進行する丸め、第１図の如
くジャストエツチングにおいては端面３に若干チーｉ４
がついたツヤターン４を形成できる。しかしながら、実
際には、このジャストエツチングが難しく、Ｍ板全面で
のエツチングムラをカバーするために％ある程度のオー
バエツチングをしなければならず、第２図に示す如く端
面３′が垂直に近いツヤターン４′となりてしまり。ま
た、かかる等方性エツチングではエツチングのムラやオ
ーバが直接、ノ帯ターン寸法に影４９するため、寸法精
度の厳しいパターンにおいては、等方性エツチングの使
用は不向きとなる。That is, in the case of plasma etching, which is isotropic etching, a mask material (
For example, the film to be etched exposed from the reso- ton's arm turn) 2 is rounded so that the etching progresses isotropically, and as shown in Fig.
A glossy turn 4 can be formed. However, in reality, this just etching is difficult, and in order to cover the etching unevenness on the entire surface of the M board, it is necessary to over-etch to a certain extent. It ended up being 4'. Further, in such isotropic etching, unevenness or over-etching directly affects the band turn dimensions, so isotropic etching is not suitable for patterns with strict dimensional accuracy.
これに対し、本発明者は上記問題を克服すべく鋭意研究
を重ねた結果、基板上の被エツチング膜をマスク材を用
いてエツチングする際、始めに等方性エツチングで処理
してマスク材から露出する被エツチング膜の一部が残る
ようにエツチングして端面をチー・膏にした後、非等方
性エツチング、（例えばリアヶティプイオンエ。On the other hand, as a result of extensive research in order to overcome the above-mentioned problems, the inventor of the present invention has found that when etching a film to be etched on a substrate using a mask material, it is first processed by isotropic etching to remove the film from the mask material. After etching so that a part of the film to be etched remains exposed to make the end surface a plaster, anisotropic etching is performed (for example, rear tip etching).
チング）で処理して残存した薄い被エツチング膜を完全
に除去することによって、テーノ臂の付いた断面形状を
有し、かつ寸法精度の良好な・９ターンを形成し得る方
法を見い出した。We have found a method that can form nine turns with a tenon-shaped cross section and good dimensional accuracy by completely removing the remaining thin film to be etched.
すなわち、本発明は基板上に被エツチング膜を被着する
工程と、この被エツチング膜上にマスク材を選択的に形
成する工程と、このマスク材を用いて前記基エツチング
膜を少なくともマスク材から露出する部分に薄い被エツ
チング膜が残存するように等方性エツチングを行なう工
程と、前記マスク材を用いて露出する残在した薄い被エ
ツチング膜を非等方性エツチングにょル完全に除去する
工程とを具１藷したことを特徴とするものである。That is, the present invention includes a step of depositing a film to be etched on a substrate, a step of selectively forming a mask material on the film to be etched, and a step of selectively forming a mask material on the film to be etched, and etching the base etching film from at least the mask material using the mask material. A step of performing isotropic etching so that a thin film to be etched remains on the exposed portion, and a step of completely removing the remaining thin film to be etched exposed by anisotropic etching using the mask material. It is characterized by having one ingredient.
本発明に用いる基板としては、例えばｐ型もしくはｍ型
のシリコン基板、シリコン基板上に工♂り中シャル層を
成長させた基板、或いはサファイアナトの絶縁基板上に
エビタ中シャル層を成長させた基体等を挙げることがで
きる。The substrate used in the present invention may be, for example, a p-type or m-type silicon substrate, a substrate on which a silicon layer is grown during processing, or a sapphire insulating substrate on which an Evita crystal layer is grown. Examples include a substrate.
本発明に用いる被エツチング膜としては、例えばｒ−）
電極や配線となる本綿物Ｐ−プ多結晶シリコン膜、金属
シリサイド膜、もしくはｍ、ｐｔ、ｗなどの金属膜、又
は層間絶縁膜やノ９ツシペーシーン膜となるＣＶＤ −
５ｔｏ２ＪｌＫ、燐硅化ガラス膜（ＰＳＧ膜）、シリコ
ン窒化膜、アルンナ膜等を挙げる仁とができる。Examples of the film to be etched used in the present invention include r-)
A real cotton P-polycrystalline silicon film, a metal silicide film, or a metal film such as m, pt, or w, which becomes an electrode or wiring, or a CVD film which becomes an interlayer insulating film or a space film.
5to2JlK, phosphorus silicide glass film (PSG film), silicon nitride film, Aluna film, etc. can be used.
本発明における等方性エツチングは／４ターンの端面（
段差部）をチー／ｌ状にするために行なうものである。In the present invention, isotropic etching is performed on the end face of /4 turn (
This is done to make the step part) into a chi/l shape.
かかる等方性エツチングとしては例えばグッズマエッチ
ング法を挙げることができる。Examples of such isotropic etching include Goodsma etching.
本発明における非等方性エツチングは、マスク材に忠実
な高精度のパターンを形成するために行なう。かかるエ
ツチング手段としては、例えばリアクティブイオンエツ
チング、反応性イオンビームエツチング等を挙げること
ができる・次に、本発明のパターン形成方法を２層ｒ
−ト構造を有するＭＯＳダイナミ、りＲＡＭに適用した
例について第３図（ａ）〜（・）を参照して説明する。Anisotropic etching in the present invention is performed to form a highly accurate pattern faithful to the mask material. Examples of such etching means include reactive ion etching, reactive ion beam etching, etc.Next, the pattern forming method of the present invention is applied to two layers.
An example in which the present invention is applied to a MOS dynamic RAM having a gate structure will be described with reference to FIGS.
実施例
〔１〕まず、ｐ型シリコン基板１１に素子領域を分離す
る九めの厚さ１μｍのフィールド酸化膜１２を選択酸化
法によ〕形成した後、１０００℃のドライ酸素雰囲気中
で熱酸化処理してキヤ・ヤシタ予定領域に厚さ３００Ｘ
のシリコン酸化膜１３を成長した拳つづいて、制御ｆ−
）電極となる厚さ４００ Ｇ ！、 リン濃度Ｉ Ｘ
１０”／ｃＩ１１５のリンドーゾ多結晶シリコン膜１
４を全面に堆積した後、制御ダート電極形成予定部上に
写真蝕刻法によシレジスト・り−７１５を形成した（第
３図（、）図示）。Example [1] First, a field oxide film 12 with a thickness of 1 μm is formed on a p-type silicon substrate 11 to separate device regions by selective oxidation method], and then thermal oxidation is performed in a dry oxygen atmosphere at 1000°C. Process and apply thickness 300X to the planned area
After growing the silicon oxide film 13, the control f-
) Thickness 400G for electrode! , phosphorus concentration I
10"/cI115 lindozo polycrystalline silicon film 1
4 was deposited on the entire surface, a resist layer 715 was formed by photolithography on the area where the control dart electrode was to be formed (as shown in FIG. 3(a)).
（ｉｉ）次いで、シリコン基板１ノをエツチング装置の
真空チャンバ円に入れ、チャンバＶ′３ｔ−ＣＦ４：０
２がｌ：ｌでＱ、 ｌ Ｔｏｒｒの雰囲気にし、１３．
５６ＭＨ，の高周波を印加してレゾストノ母ターン１５
から露出するリンドーグ多結晶シリコン膜１４を３０秒
間！ラズマエ、チングシタ、この時、レノスト／々ター
ン１５下のリンドーグ多Ｍ晶シｌＪ：ｒン膜１４が等方
的にエツチングされチーΔ状となると共にレジストノナ
ターン１５がら露出する部分に厚さ約８００Ｘの多結晶
シリコン膜１４′が残存した（第３図（ｂ）図示）、つ
づいて真空チャ７２円の雰囲気をＣＢｒ、 ？、 ：
Ｃｔ２がｌ：３て０． Ｉ Ｔ＠ｒｔに変え、反応性イ
オンエツチングを２分３０秒間行なった。この時、第３
図（、）に示す如くレジストパターン１５から霧出する
残存多結晶シリコン膜１４′のみが完全にエツチング除
去され、略端面１６全体ＩＥりぐ状をなす制御ｒ−）電
極１７が形成され友。(ii) Next, put the silicon substrate 1 into the vacuum chamber circle of the etching device, and chamber V'3t-CF4:0
2 is l:l and Q, l Torr atmosphere, 13.
Applying a high frequency of 56MH, the resistance mother turn 15
30 seconds to expose the Lindog polycrystalline silicon film 14! At this time, the lindog poly-M crystalline film 14 under the resist/naturn 15 is isotropically etched to form a chi Δ shape, and the exposed portion of the resist nonaturn 15 has a thickness of approximately After the 800X polycrystalline silicon film 14' remained (as shown in FIG. 3(b)), the atmosphere of the vacuum chamber 72 was changed to CBr. , :
Ct2 is l:3 and 0. Reactive ion etching was performed for 2 minutes and 30 seconds by changing to IT@rt. At this time, the third
As shown in FIG. 3(a), only the remaining polycrystalline silicon film 14' sprayed out from the resist pattern 15 is completely etched away, and a control r-) electrode 17 having an IE groove shape is formed on substantially the entire end surface 16.
Ｃ１１ｉ〕次いで、制御ｒ−ト電極１７をマスクとして
トランジスタ部の熱酸化膜（図示せず）をエツチングし
、更に８００Ｃのクエ、ト酸素雰囲気中で熱酸化処理し
た。この時、第３図（ｄ）に示す如く制御ｒ−）電極１
７の周囲に層間絶縁膜１８が形成されると共に該電極１
１の端面１６の層間絶縁膜１８部分はオーバハングのな
い良好なテーノ譬状となった。つづいて厚さ４０００Ｘ
のモリブデンシリサイド膜を堆積し、こレヲ／＃ターニ
ングしてキャノ譬シタ電極１９を形成し７？：（第３図
（−図示）。その後、常法に従ってＭＯ８）ランジスタ
の形成、コンタクトホールの開孔、Ａｔ配線の形成を行
なってＭＯＢダイナミック勧Ｍを装造した・
しかして、本発明によれば制御ｒ−）電極の形成に除し
て等方性エツチング法と非等方性工、チング法を組合わ
せてリンドーグ多結晶シリコン１４全Δターニングする
ことによってテーノ母状の端面１６を有すると共にレジ
スト・９ターフ１５に忠実な高精度の制御ダート電極１
１を形成できる。その結果、該電極１７の熱酸化によ多
形成された層間絶縁膜１８は区電極１１の端面に対応す
る部分がオーバハング構造とならずテーノ臂状となシ、
こζを横切るキャーシタ電極１９の段切れを防止できる
。したがって微細で高信頼性のＭＯＳダイナミ、りＲＡ
Ｍ ’ｉ得ることができる。C11i] Next, using the control electrode 17 as a mask, the thermal oxide film (not shown) of the transistor portion was etched, and further thermal oxidation treatment was performed in an oxygen atmosphere at 800C. At this time, as shown in FIG. 3(d), the control r-) electrode 1
An interlayer insulating film 18 is formed around the electrode 1 .
The portion of the interlayer insulating film 18 on the end surface 16 of No. 1 had a good shape with no overhang. Next, thickness 4000X
A molybdenum silicide film is deposited and turned to form a capacitor electrode 19 (7). : (Fig. 3 (-illustration). After that, according to the conventional method, the MOB dynamic conductor was fabricated by forming transistors, forming contact holes, and forming At wirings.) According to the present invention, Control r-) During electrode formation, the Lindor polycrystalline silicon 14 is completely Δ-turned by combining isotropic etching, anisotropic etching, and etching to form a Theno matrix-like end surface 16. High precision control dart electrode 1 faithful to resist 9 turf 15
1 can be formed. As a result, the interlayer insulating film 18 formed by thermal oxidation of the electrode 17 does not have an overhanging structure at the portion corresponding to the end surface of the electrode 11, but has an arch-like structure.
It is possible to prevent the capacitor electrode 19 from breaking across this ζ. Therefore, fine and highly reliable MOS dynamics, RIRA
M'i can be obtained.
なお、リンドーノ多結晶シリコン膜１４０等方性工、チ
ンダ（プラズマエッチング）は上記実施例の如くレジス
トパターン１５から無比する部分に厚さ８００Ｘの多結
晶シリコン膜１４′を残存させるように行なう場合に限
定されない。Incidentally, in the case where the isotropic etching and etching (plasma etching) of the Lindono polycrystalline silicon film 140 are performed so as to leave the polycrystalline silicon film 14' with a thickness of 800× in a portion far away from the resist pattern 15 as in the above embodiment, Not limited.
例えば、第４図（、）に示す如くプラズマエツチング時
間を短かくして残存多結晶シリコン膜１４″を厚くして
もよい。この場合、プラズマエツチング後に反応性イオ
ンエツチング処理を行なう仁とによって、第４図（ｂ）
に示す如く端面１６′が実施例のものよシややテーパが
小さい制御ダート電極１７′が形成される。ｉた、第５
図（ａ）に示す如くグラズｉエツチング時間を長くして
残存多結晶シリコン膜１４１１１を薄くしてもよい。こ
Ｏ場合、プラズマエツチング後に反応性イオンエツチン
グを行なうことによって、第５図（ｂ）に示す如く端面
１６′が実施例のものよシテー／４’が大きいが、やや
精度の点で劣る制御ｆ−）電極１１′が形成される。For example, the remaining polycrystalline silicon film 14'' may be thickened by shortening the plasma etching time as shown in FIG. Figure (b)
As shown in FIG. 2, a control dart electrode 17' is formed whose end surface 16' has a smaller shear and taper than that of the embodiment. 5th
The remaining polycrystalline silicon film 14111 may be made thinner by lengthening the glaze etching time as shown in FIG. 3(a). In this case, by performing reactive ion etching after plasma etching, the end face 16' has a larger city/4' than that of the embodiment, as shown in FIG. 5(b), but the control f is slightly inferior in terms of accuracy. -) Electrode 11' is formed.
以上詳述した如く、本発明によればチー・ぐの付いた断
面形状を有し、かつ寸法精度の良好なノ母ターンを形成
でき、もって半導体装置の第１層電極配線等の形成に適
用した場合、この上を横切る第２層−極配線を段切れを
防止でき、高信頼性と高集積化を達成できる等顕著な効
果を有する。As described in detail above, according to the present invention, it is possible to form a main turn having a cross-sectional shape with a groove and good dimensional accuracy, and thus it is applicable to the formation of first layer electrode wiring of semiconductor devices, etc. In this case, it is possible to prevent the second layer-electrode wiring that crosses this from breaking, and it has remarkable effects such as achieving high reliability and high integration.
第１図、第２図は夫々従来の等方性エツチングのみで行
なったパターンの断面図、第３図（ａ）〜（・）は本発
明の実施例における２層ｒ−）構造を有するＭＯ８ダイ
ナミックＲＡＭの製造を示す工程断面図、第４図（ａ）
、 （ｂ）及び第５図（ａ） 、 （ｂ）は夫夫第３
図の制御ｒ−）電極を形成するための変形例を示す工程
断面図である。
１１・・・ｐｆｆｌシリコン基板、１２・・・フィール
ド酸化膜、１３・・・シリコン酸化膜、１４・・・リン
ドーグ多結晶シリコン膜、１４’、１４’、１４’ ・
・・残存多結晶シリコンｋ、ｚｓ・・・レジストパター
ン、１６．１６’、１６“・・・端面、７７．１７’。
１７’・・・制御ダート電極、１８・・・層間絶縁膜、
１９・・・キヤｒｋｈ？−νり電極。
出願人代理人 弁理士 鈴 江 武 彦第１図
特許庁長官 島 １）春 樹 殿
１．事件の表示
特願昭５６−１１５７８６号
２、発明の名称
ノ臂ターン形成方法
３、補！Ｅをする者
事件との関係 特許出願人
（３０７） 東京芝浦電気株式会社
４、代理人
住所 東京都港〆虎ノ門１丁目２６１５号 第１７森ビ
ル〒１０５ 電品０３ （５０２） ３１８１ （
大代表）耐相５６年１１月２４日
６、補正の対象
（ｂ）と訂正する。FIGS. 1 and 2 are cross-sectional views of patterns made only by conventional isotropic etching, and FIGS. 3(a) to (·) are MO8 having a two-layer r-) structure in an embodiment of the present invention. Process sectional view showing the manufacturing of dynamic RAM, FIG. 4(a)
, (b) and Fig. 5 (a), (b) are
FIG. 6 is a process sectional view showing a modification example for forming the control r-) electrode in the figure. 11... pffl silicon substrate, 12... field oxide film, 13... silicon oxide film, 14... Lindog polycrystalline silicon film, 14', 14', 14'.
...Residual polycrystalline silicon k, zs...Resist pattern, 16.16', 16"...End face, 77.17'. 17'...Control dart electrode, 18...Interlayer insulating film,
19...kiya rkh? −ν electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Commissioner of the Patent Office Shima 1) Haruki Tono 1. Indication of the case Japanese Patent Application No. 56-115786 2, Title of the Invention: Method for Forming Arm Turn 3, Supplement! Relationship with the case of the person committing E Patent applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, agent address 17th Mori Building, 1-2615 Toranomon, Minato, Tokyo 105 Electrical Products 03 (502) 3181 (
Main Representative) November 24, 1956, 6, amended to subject to amendment (b).
Claims (1)
チング膜上にマスク材を選択的に形成する工程と、この
マスク材を用いて前記被エツチング膜を少なくともマス
ク材から露出する部分に薄い被エツチング膜が残存する
ように等方性工、チングを行なう工程と、前記マスク材
を用いて露出する残存した薄い被エツチング膜を非等方
性工、チングによシ完全に除去する工程とｔ具備したこ
とを特徴とするノ９ターン形成方法。a step of depositing a film to be etched on a substrate; a step of selectively forming a mask material on the film to be etched; A step of performing isotropic processing and etching so that the film to be etched remains; and a step of completely removing the remaining thin film to be etched exposed using the mask material by anisotropic processing and etching. A method for forming nine turns, characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11578681A JPS5817619A (en) | 1981-07-23 | 1981-07-23 | Forming method for pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11578681A JPS5817619A (en) | 1981-07-23 | 1981-07-23 | Forming method for pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5817619A true JPS5817619A (en) | 1983-02-01 |
Family
ID=14671026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11578681A Pending JPS5817619A (en) | 1981-07-23 | 1981-07-23 | Forming method for pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5817619A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457623A (en) * | 1987-08-28 | 1989-03-03 | Toshiba Corp | Manufacture of semiconductor device |
| US5006480A (en) * | 1988-08-08 | 1991-04-09 | Hughes Aircraft Company | Metal gate capacitor fabricated with a silicon gate MOS process |
| US5108941A (en) * | 1986-12-05 | 1992-04-28 | Texas Instrument Incorporated | Method of making metal-to-polysilicon capacitor |
| US6376383B2 (en) | 1998-01-16 | 2002-04-23 | Nec Corporation | Method for etching silicon layer |
| US9269765B2 (en) | 2013-10-21 | 2016-02-23 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device having gate wire disposed on roughened field insulating film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5687666A (en) * | 1979-12-20 | 1981-07-16 | Toshiba Corp | Plasma etching method |
| JPS5690525A (en) * | 1979-11-28 | 1981-07-22 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-07-23 JP JP11578681A patent/JPS5817619A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5690525A (en) * | 1979-11-28 | 1981-07-22 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5687666A (en) * | 1979-12-20 | 1981-07-16 | Toshiba Corp | Plasma etching method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5108941A (en) * | 1986-12-05 | 1992-04-28 | Texas Instrument Incorporated | Method of making metal-to-polysilicon capacitor |
| JPS6457623A (en) * | 1987-08-28 | 1989-03-03 | Toshiba Corp | Manufacture of semiconductor device |
| US5006480A (en) * | 1988-08-08 | 1991-04-09 | Hughes Aircraft Company | Metal gate capacitor fabricated with a silicon gate MOS process |
| US6376383B2 (en) | 1998-01-16 | 2002-04-23 | Nec Corporation | Method for etching silicon layer |
| US9269765B2 (en) | 2013-10-21 | 2016-02-23 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device having gate wire disposed on roughened field insulating film |
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