JPS58175200A - Checking system of storage system - Google Patents

Checking system of storage system

Info

Publication number
JPS58175200A
JPS58175200A JP57058808A JP5880882A JPS58175200A JP S58175200 A JPS58175200 A JP S58175200A JP 57058808 A JP57058808 A JP 57058808A JP 5880882 A JP5880882 A JP 5880882A JP S58175200 A JPS58175200 A JP S58175200A
Authority
JP
Japan
Prior art keywords
write data
bit
error correction
storage device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57058808A
Other languages
Japanese (ja)
Other versions
JPS6235703B2 (en
Inventor
Shigeru Miyajima
茂 宮島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57058808A priority Critical patent/JPS58175200A/en
Publication of JPS58175200A publication Critical patent/JPS58175200A/en
Publication of JPS6235703B2 publication Critical patent/JPS6235703B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To prevent an increase in cost of a storage system, by providing a gate circuit, which makes write data of all ''0'' or all ''1'' forcibly, between a write data register and a storage device to check every bit in an error correcting circuit. CONSTITUTION:In the normal use, (a) is logical ''1'' and (b) is logical ''0'', and write data is inputted to a storage device 4 as it is. In case that bit 0 is checked, data where only bit 0 is ''0'' and other bits are ''1'' is set to a write data register 1, and (b) is set to logical ''1'', and data is written. An error correction code generating circuit 3 generates a code for this data, and this code is written in the storage device 4. Meanwhile, since data written actually in the storage device 4 is all ''1'', write data is written with only bit 0 inverted equivalently as the result. It is checked whether the bit position coincides with the position of the inverted bit or not to check the operation of an error correcting circuit.

Description

【発明の詳細な説明】 〔発明の分野〕 本発明は記憶システムにおける誤り訂正回路のチェック
方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a checking method for error correction circuits in storage systems.

〔従来技術とその問題点〕[Prior art and its problems]

一般に、誤り訂正回路が正常に動作するか否かをチェッ
クするには、データ部又は誤り訂正コード部のいずれか
を誤らせて書込ませ、読出しデータにてその誤りが正し
く検出され、かつ訂正されるか否かをチェックすればよ
い。Generally, to check whether an error correction circuit operates normally, write an error in either the data section or the error correction code section, and make sure that the error is correctly detected in the read data and corrected. Just check whether it is done or not.

しかし、十分なチェックを行うにはデータ部及び誤り訂
正コード部の任意のビットについてその値を反転する回
路が必要となり、金物量を多く　Ｊ・要とする欠点があ
った。（即ち、ビット位置を指定するためのレジスタ、
そのレジスタの内容をデコードするデコーダ、及びＥＯ
Ｒゲートなどが必要） 〔発明の目的〕 本発明の目的は、任意のビットについてのチェックを簡
単な回路で可能とすることにある。However, in order to perform a sufficient check, a circuit is required to invert the value of any bit in the data section and error correction code section, which has the drawback of requiring a large amount of hardware. (i.e., a register for specifying the bit position,
a decoder that decodes the contents of that register, and an EO
(Requires R gate, etc.) [Object of the Invention] An object of the present invention is to enable checking of arbitrary bits with a simple circuit.

〔発明の実施例〕[Embodiments of the invention]

また、ａは書込みデータをオール“０−するための信号
５　ｂは書込みデータをオール“１″とするための信号
である。Further, a is a signal 5 for setting the write data to all "0-", and b is a signal for setting the write data to all "1".

さらに、第２図はゲート回路の一実施例回路図であり、
　２１．２１．・−・はＡＮＤゲート、　２２．２２．
山はＯＲゲートである。Furthermore, FIG. 2 is a circuit diagram of one embodiment of the gate circuit,
21.21. ... is an AND gate, 22.22.
The mountain is an OR gate.

通常の使用時には、ａは論理“ｌ”、ｂは論理“０”で
あり、書込みデータはそのまま記憶装置４に入力される
。During normal use, a is at logic "1" and b is at logic "0", and the write data is input to the storage device 4 as is.

チェック時には２例えばビット０をチェックするには、
書込みデータ・レジスタｌにビット０のみがθ′で他の
ビットは“ビであるデータをセットしておき、ｂｔ−論
理″１”として書込みを行わせる。誤り訂正コード作成
回路３はビット０のみが“Ｏ”で他のビ・７トは１°で
あるデータに対するコードを作成し、それが記憶装置４
に書込まれる。一方、実際に記憶装置４に書込まれるデ
ータはオール“１″であるから、結果的には書込みデー
タのビット０のみを反転して書込んだことと等価となる
。2 when checking For example, to check bit 0,
Set data in which only bit 0 is θ' and other bits are "bi" in the write data register l, and write as bt-logic "1".The error correction code generation circuit 3 only has bit 0. is “O” and the other bits are 1°, and it is stored in storage device 4.
written to. On the other hand, since the data actually written to the storage device 4 is all "1", the result is equivalent to inverting and writing only bit 0 of the write data.

読出しデータに誤りが有るか否か、及びどのビットに誤
りが生しているかは、誤り訂正回路で作成されるシンド
ロームを見ることにより９判明する。よってそのピント
位置が前記反転した（等価的に）ビットと一致するか否
かを調べれば、誤り訂正回路の動作チェックをすること
ができる。Whether or not there is an error in the read data and in which bit the error occurs can be determined by looking at the syndrome created by the error correction circuit. Therefore, by checking whether the focus position matches (equivalently) the inverted bit, the operation of the error correction circuit can be checked.

以下同様にして、任意のデータ・ビットについてそのビ
ットのみが“０″又は“１″である書込みデータを書込
みデータ・レジスタ１にセントし。Thereafter, write data in which only the arbitrary data bit is "0" or "1" is sent to the write data register 1 in the same manner.

さらにａまたはｂを操作することにより、任意の１ビツ
トのみを反転させたと同様なチェックが可能となる。Furthermore, by manipulating a or b, it becomes possible to perform a check similar to inverting only one arbitrary bit.

以上のような書込みデータ・レジスタｌへのデータのセ
ントや、信号ａまたはｂを操作することはマイクロ・プ
ログラム制御によって容易に実行可能である。Writing data to write data register l and manipulating signal a or b as described above can be easily executed by microprogram control.

〔発明の効果〕〔Effect of the invention〕

以上のとうり１本発明によれば第２図のような簡単なゲ
ート回路を設けることにより、誤り訂正回路のビット毎
のチェックが可能であり、記憶システムのコスト・アン
プを防止するとともに、十分なＲＡＳ機能を持たせるこ
とを可能とする。According to the present invention, by providing a simple gate circuit as shown in FIG. 2, it is possible to check each bit of the error correction circuit. This makes it possible to have a RAS function.

【図面の簡単な説明】[Brief explanation of drawings]

十１図は本発明における記憶システムの一実施例ブロッ
ク図であり、ｌは書込みデータ・レジスタ。 ２はゲート回路、３は誤り訂正コード作成回路。 ４は記憶装置５５は誤り訂正回路、６は読出しデータ・
レジスタである。 第２図はゲート回路の一実施例回路図であり。 ２１、２１．−−・はＡＮＤゲート、　２２．、２２．
−はＯＲゲートである。 （５） 躬　１　　図 第　Ｚ　　図FIG. 11 is a block diagram of an embodiment of the storage system according to the present invention, where l is a write data register. 2 is a gate circuit, and 3 is an error correction code generation circuit. 4 is a storage device 55 which is an error correction circuit, 6 is a read data
It is a register. FIG. 2 is a circuit diagram of one embodiment of the gate circuit. 21, 21. --・ is an AND gate, 22. , 22.
- is an OR gate. (5) Error 1 Figure Z

Claims (1)

【特許請求の範囲】 書込みデータ・レジスタと、該書込みデータ・レジスタ
の内容に対する誤り訂正コードを作成する誤り訂正コー
ド作成回路と、前記書込みデータと前記誤り訂正コート
とを対にして記憶する記憶装置と、該記憶装置からの読
出しデータに対して誤り訂正を行う誤り訂正回路とを有
する記憶システムにおいて。 前記書込みデータ・レジスタと前記記憶装置との間に、
書込みデータを強制的にオール“０”。 又はオール“ｌ”にするゲート回路を設け、前記書込み
データ・レジスタにオール“ｏ′、又はオール“Ｏ”以
外の所定のデータをセントし、前記ゲート回路により書
込みデータをオール“０″。 又はオール“１”として書込みを行わせることにより、
前記記憶装置に対してデータ部と誤り訂正コード部との
対応を誤らせて書込ませ、もって誤り訂正回路の動作を
チェックすることを特徴とする記憶システムのチェック
方式。[Scope of Claims] A write data register, an error correction code creation circuit that creates an error correction code for the contents of the write data register, and a storage device that stores the write data and the error correction code as a pair. and an error correction circuit that performs error correction on data read from the storage device. between the write data register and the storage device;
Force all write data to “0”. Alternatively, a gate circuit is provided to set all "L", and all "O'" or predetermined data other than all "O" is sent to the write data register, and the write data is set to all "0" by the gate circuit. By writing as all “1”,
A checking method for a storage system, characterized in that the operation of an error correction circuit is checked by causing the storage device to write data with an incorrect correspondence between a data section and an error correction code section.
JP57058808A 1982-04-08 1982-04-08 Checking system of storage system Granted JPS58175200A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57058808A JPS58175200A (en) 1982-04-08 1982-04-08 Checking system of storage system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57058808A JPS58175200A (en) 1982-04-08 1982-04-08 Checking system of storage system

Publications (2)

Publication Number Publication Date
JPS58175200A true JPS58175200A (en) 1983-10-14
JPS6235703B2 JPS6235703B2 (en) 1987-08-03

Family

ID=13094897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57058808A Granted JPS58175200A (en) 1982-04-08 1982-04-08 Checking system of storage system

Country Status (1)

Country Link
JP (1) JPS58175200A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139857A (en) * 1984-12-12 1986-06-27 Fujitsu Ltd Inspection system for memory circuit
JPH0414149A (en) * 1990-05-08 1992-01-20 Yamatake Honeywell Co Ltd Test device for parity check circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5294744A (en) * 1976-02-04 1977-08-09 Hitachi Ltd Diagnosis system for error detection and correction circuits
JPS5425637A (en) * 1977-07-29 1979-02-26 Fujitsu Ltd Memory unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5294744A (en) * 1976-02-04 1977-08-09 Hitachi Ltd Diagnosis system for error detection and correction circuits
JPS5425637A (en) * 1977-07-29 1979-02-26 Fujitsu Ltd Memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139857A (en) * 1984-12-12 1986-06-27 Fujitsu Ltd Inspection system for memory circuit
JPH0414149A (en) * 1990-05-08 1992-01-20 Yamatake Honeywell Co Ltd Test device for parity check circuit

Also Published As

Publication number Publication date
JPS6235703B2 (en) 1987-08-03

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