JPS58163434A - Plasma gas phase reaction method - Google Patents

Plasma gas phase reaction method

Info

Publication number
JPS58163434A
JPS58163434A JP4783282A JP4783282A JPS58163434A JP S58163434 A JPS58163434 A JP S58163434A JP 4783282 A JP4783282 A JP 4783282A JP 4783282 A JP4783282 A JP 4783282A JP S58163434 A JPS58163434 A JP S58163434A
Authority
JP
Japan
Prior art keywords
discharge
electric energy
plasma
phase reaction
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4783282A
Other languages
Japanese (ja)
Other versions
JPS634449B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP4783282A priority Critical patent/JPS58163434A/en
Publication of JPS58163434A publication Critical patent/JPS58163434A/en
Publication of JPS634449B2 publication Critical patent/JPS634449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B01PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01JCHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS OR COLLOID CHEMISTRY; THEIR RELEVANT APPARATUS
    • B01J15/00Chemical processes in general for reacting gaseous media with non-particulate solids, e.g. sheet material; Apparatus specially adapted therefor

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

PURPOSE:To protect a surface to be formed from damages, by a method wherein initial electric discharge is carried out at low applied voltage by an auxiliary circuit and the impedance between capacitive discharge electrodes is synchronized while low electric energy is supplied to said electrodes. CONSTITUTION:A plasma gas phase reaction furnace 2 is filled with a reactive gas to establish predetermined pressure. In the next step, low electric energy is supplied for matching and an auxiliary circuit 5 based on the inductance component of current drive is subjected to initial electric discharge. Succeedingly, low electric energy lower than electric energy carrying out plasma gas phase reaction is supplied to a pair of capacitive discharge electrodes 3, 4. While this electric energy is supplied, the impedance between the electrodes is synchronized and predetermined electric energy carrying out plasma gas phase reaction is supplied. Thereby, the surface formed on the substrate 1 is protected from damages.

Description

【発明の詳細な説明】 本発明はグローまたはアーク放電を利用したプラズマ気
相法(以下POVDとする)を実施するためのプラズマ
反応炉に対して、プラズマ放電のソフトスタートを再現
性よ〈実施せしめるプラズマ反応用装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for reproducibly implementing a soft start of plasma discharge for a plasma reactor for implementing a plasma vapor phase method (hereinafter referred to as POVD) using glow or arc discharge. The present invention relates to an apparatus for plasma reaction.

本発明はPCVDを行なう場合、一般にPC!VD装置
内に被形成面を有する基板を配置せしめ、一度1×10
〜10torrに真空引をし、この後この中の真空度を
0.05〜3torrに反応性気体を導入して成就する
。そしてこの反応性気体を外部より所定の出力の電気エ
ネルギを一対を構成する電極を与えてプラズマ放電をせ
しめ、とのプラズマ化した反応性気体よシの反応生成物
を被形成面上に形成せしめるものである。
In the present invention, when performing PCVD, generally PC! Place the substrate with the surface to be formed in the VD equipment, and once
A vacuum is drawn to ~10 torr, and then a reactive gas is introduced to bring the vacuum level within the vacuum to 0.05 to 3 torr. Then, electrical energy of a predetermined output is applied to this reactive gas from the outside to a pair of electrodes to cause plasma discharge, and a reaction product of the reactive gas and the plasma is formed on the surface to be formed. It is something.

しかし実際にかかるtf、 flを行なってみるとこの
通シにはならない。そして電気エネルギを所定の出力で
与えようとした時、特にその電気エネルギを50W以下
の低いエネルギで与えようとした時、このプラズマ放電
がおこらない。このため例えば5〜10Wのプラズマ出
力を加えようとする時、一度放電を開始させるため20
〜30Wに出力をあげ放電をした後、その出力を5〜1
0Wに小さくするという作業をせざるを得なかった。
However, when such tf and fl are actually performed, this general rule does not hold. When attempting to apply electrical energy at a predetermined output, especially when attempting to apply electrical energy at a low energy of 50 W or less, this plasma discharge does not occur. For this reason, when trying to apply a plasma output of 5 to 10 W, for example, 20 W is required to start the discharge.
After increasing the output to ~30W and discharging, reduce the output to 5~1
I had no choice but to reduce the power to 0W.

さらにこの高周波出力を反応性気体に与えようとする時
、その間での同調(マツチング)が必要である。しかし
このマツチングは放電をしない限シ、また電気エネルギ
を与えない限り、同調点を見出すことができない。
Furthermore, when trying to apply this high frequency output to a reactive gas, matching is required between them. However, this matching cannot find a matching point unless electric discharge is performed or electric energy is applied.

このためオート’(ツチング方式のPCVD装置であっ
ても、■一度高い出力を加えて放電をさせた後、■マツ
チング点をさがし、さらに、■所定の出力にまで供給電
気エネルギを下げる。
For this reason, even if the PCVD apparatus is an auto' (touching method), 1) once a high output is applied to cause discharge, 2) a matching point is found, and 2) the supplied electrical energy is lowered to a predetermined output.

という作業が必要であった。This work was necessary.

しかしこの作業はPCVD法によシ透明導電膜4’l、
寧2・・Φ 上に薄でT11層を積層し、さらにこの半導体層のそれ
ぞれに添加された不純物のお互いへの囁 Y人をさけんとする時、きわめて大きな障害となる0特
に一定の高い出力でマツチング点をさがす数秒の間に、
また−マツチングがとれた瞬間の過1撲亀中にこの高い
エネルギが被形成面をスパッタ(損傷)シ、その被形成
面の表面を5〜100Aのショートレンジオーダでも不
秩序性をもたらしてしまう。このためこの界面での再結
合中心が増加し、半導体により透明導電膜4工Nくなっ
てしまう。またさらに工型半導体層を作製しようとする
時、との工層中にP型半導体中門1 20〜30Wより5〜10Wに下げるまでの  におい
て、高い放電エネルギにて被形成面上に半導体層が形成
され、このためf5q 4 #・K1層を作っている間
にこの出力により透明導電膜が基板のガラス面よシはか
れたシ、また工To(酸化インジューム・スズ合金)に
おいて、酸素が遊離し金属インジュームが析出して白濁
化現象がみられた0本発明はかかる欠点を除くためにな
されたものであって、プラズマOvDの放電が2〜5W
においても、何ら支障な〈実施させるように、放電助長
用のコイルまたは配線を一対を構成する容量性電極間に
設けたものである。
However, this work is carried out using the PCVD method.
N2...Φ A thin T11 layer is laminated on top of the semiconductor layer, and impurities added to each of these semiconductor layers whisper to each other. In the few seconds it takes to find the matching point,
In addition, during the moment of unmatching, this high energy sputters (damages) the formed surface, causing disorder even in the short range order of 5 to 100 A. . Therefore, the number of recombination centers at this interface increases, and the transparent conductive film becomes 4 N thick due to the semiconductor. Furthermore, when attempting to fabricate a semiconductor layer, a high discharge energy is used to form a semiconductor layer on the surface to be formed. was formed, and for this reason, the transparent conductive film was peeled off from the glass surface of the substrate due to this output while the f5q 4 # K1 layer was being made. was liberated and metal indium precipitated, resulting in a clouding phenomenon.The present invention was made to eliminate such drawbacks, and the plasma OvD discharge is 2-5W
However, in order to avoid any problems, a coil or wiring for promoting discharge is provided between a pair of capacitive electrodes.

さらにマツチングに関しては、PCVDを5〜10Wで
行なわんとした時、Jbx〜2Wの低い出力を供給し、
この反応性気体におけるインピーダンスをさがしてマツ
チングをとり、この後5〜10Wの出力を引加してプラ
ズマ反応を行なわしめたことを特徴としている。
Furthermore, regarding matching, when trying to perform PCVD at 5 to 10W, it supplies a low output of Jbx to 2W,
It is characterized in that the impedance in this reactive gas is found and matched, and then an output of 5 to 10 W is applied to perform a plasma reaction.

以下に図面に従ってその詳、細を説明する。The details will be explained below according to the drawings.

第1図は本発明の動作原理を示す。FIG. 1 shows the principle of operation of the invention.

容量結合性の一対の電極(3)、(→間には、そのイン
ピーダンスおよび電極間抵抗を放電前Z c、R。
A pair of capacitively coupled electrodes (3), (→ between them, their impedance and interelectrode resistance are Z c, R before discharge.

放電中Z c’、R’とし、またその時を13.56Q
Hz等の周波数(時定数をω)とすると Z c = Rf7− ノωC 但しR))R そしてこのリタクタンス成分である 1/ノ゛ω1Cを
相殺するように+jω−をマツチング回路にて与える。
During discharge Z c', R' and the time is 13.56Q
When a frequency such as Hz (time constant is ω), Z c = Rf7− ωC (where R))R and +jω− is applied by a matching circuit so as to cancel out this retance component 1/ω1C.

するとインピーダンス成分はZa=Rと抵抗成分のみと
なる。この状態がいわゆるマツチング(同調)のとれた
状態を示す0 しかしこのマツチングがとれても、必ずしも放電すると
は限らない。また放電をするとこの抵抗成分Rは反応性
気体のプラズマ化により、その抵抗はl/100または
それ以下となシ、電気エネルギ供給源(6)または00
)よシプラズマの月れのためエネルギを供給しつづける
Then, the impedance component becomes Za=R, which is only the resistance component. This state indicates a state of so-called matching (synchronization). However, even if this matching is achieved, it does not necessarily mean that a discharge will occur. Also, when a discharge occurs, this resistance component R becomes plasma due to the reactive gas, and its resistance becomes l/100 or less.
) It continues to supply energy due to the lunar rays of Yosiplasma.

またこの中間の回路にて明らかな如く、主回路と並列に
プラズマ放電助長用コイルまたはニクロムtΦ社等によ
る抵抗性(1〜300Q)配線により補助回路03)が
示されている。この回路は容量性のグロー放電法が電圧
駆動型であるため、この電極(3)(4)間は放電に必
要な電圧が印加されなければならず、また放電前の抵抗
成分(R) *十分大きいため、最初の放電を低い電気
エネルギにておこさせることがきわめて困難である。
Further, as is clear from this intermediate circuit, an auxiliary circuit 03) is shown in parallel with the main circuit by a plasma discharge promoting coil or resistive (1 to 300Q) wiring made by Nichrome tΦ or the like. Since this circuit uses a voltage-driven capacitive glow discharge method, the voltage required for discharge must be applied between the electrodes (3) and (4), and the resistance component (R) before discharge must be applied between the electrodes (3) and (4). It is large enough that it is extremely difficult to generate the first discharge with low electrical energy.

このためこの駆動回路に電流駆動のインダクタンス成分
を主とした補助回路を設けたものである。するとこの補
助回路のインピーダンスZs=r+jωLにおいて、と
のrは小さい値であるため、この補助回路に電流が流れ
、その結果この補助回路にて低い印加電圧にて初期放電
をさせることができる。するとこの放電プラズマが反応
性気体に与えることがなくなる。さらにこの主回路での
放電のf’i t: Q補助回路での放電がそのZe)
)ZaKよシ攻曙囃停止または十分小さくさせることが
重要である。すなわち Zc>Zs’)Zc !j 好ましくは Z a)>Z s>) Z c とすることが重要である。
For this reason, this drive circuit is provided with an auxiliary circuit mainly using an inductance component for current drive. Then, in the impedance Zs=r+jωL of this auxiliary circuit, since r is a small value, a current flows through this auxiliary circuit, and as a result, an initial discharge can be caused in this auxiliary circuit with a low applied voltage. Then, this discharge plasma no longer affects the reactive gas. Furthermore, the discharge in this main circuit f'i t: Q The discharge in the auxiliary circuit is its Ze)
) It is important to stop the ZaK attack or make it sufficiently small. That is, Zc>Zs')Zc! It is important to preferably satisfy Z a)>Z s>) Z c.

かくすることによシ、容量結合型の電極構造においても
、低いエネルギにてマツチング、プラズマ放電をさせる
ことがわかった。またこの補助回路C43)は一本の配
線であっても、また数回〜数百回まいたコイル構成をさ
せてもよい。
It has been found that by doing this, matching and plasma discharge can be achieved with low energy even in a capacitively coupled electrode structure. Further, this auxiliary circuit C43) may be a single wire, or may have a coil structure wound several times to several hundred times.

かくして補助回路のない従来ではみられないプラズマ気
相法における初期の被形成面のスパッタ効果を十分小さ
くさせることができた。
In this way, it was possible to sufficiently reduce the initial sputtering effect on the surface to be formed in the plasma vapor phase method, which is unprecedented in the conventional method without an auxiliary circuit.

以下にその実施例を図面に従って説明する。Examples thereof will be described below with reference to the drawings.

実施例1 第2図は本発明の筒状の反応炉を有するプラズマCVD
装置の概要を示す。
Example 1 Figure 2 shows a plasma CVD system having a cylindrical reactor according to the present invention.
An overview of the device is shown.

表面が反応性気体にょシ損傷を受けないようにしている
。さらにこの電極(3)、(4)はIE気エネルギ/7
. &f F4 (4)を有し、基板(1)は抵抗加熱
炉(〒)にょり 100〜500’Oの温度に加熱され
るようにしている。この電極(3)、(4)間にはイン
ピーダンスzcXzcが有し、この2つの電極間をコイ
ルで連結した補助回路(5)はz、Lのインピーダンス
ヲ有シテいる。
Prevents surfaces from being damaged by reactive gases. Furthermore, these electrodes (3) and (4) have IE energy/7
.. &f F4 (4), and the substrate (1) is heated to a temperature of 100 to 500'O in a resistance heating furnace (〒). An impedance zcXzc exists between the electrodes (3) and (4), and an auxiliary circuit (5) connecting these two electrodes with a coil has impedances z and L.

反応性気体は例えば非単結晶半導体を作製せんとする時
、導入口(8)よシ導出口(9)に至シ、正分調整用ニ
ードルパルプα転ストップパルプα呻ロータリーポンプ
(10)に至る。
For example, when a non-single-crystal semiconductor is being manufactured, the reactive gas is passed from the inlet (8) to the outlet (9), and then to the needle pulp for regular adjustment, the α-transfer stop pulp, and the rotary pump (10). reach.

反応性気体の導入は、例えばP工N接合を有する半導体
を作らんとする時、シランをo4よシ、流量計αQ1パ
ルプα0をへて供給される。またP型用不純物である■
価の不純物例えばTMG ()リメチルガリューム G
a (cQ、)を水素により11000PPに希釈され
たドーピングガスα→にょシ、また7価の不純物である
TMA ()リメチル7 ;/fモア 81) (OQ
)を水素を11000PPに希釈してα埠よシ供給した
。α力よシキャリアガスである水素またはへリュームを
供給した。
The reactive gas is introduced, for example, when a semiconductor having a P-N junction is to be manufactured, silane is supplied through O4, flowmeter αQ1, and pulp α0. Also, it is an impurity for P type ■
impurities such as TMG ()limethylgallium G
a (cQ,) diluted to 11000PP with hydrogen, the doping gas α→Nyoshi, and the heptavalent impurity TMA ()limethyl7;/f more 81) (OQ
) was diluted with hydrogen to 11,000 PP and supplied from α-bu. The alpha force supplied hydrogen or helium, which is a carrier gas.

かくして基板上に工T O,酸化スズ(酸化アンチモン
が2〜10チ添加された)透明導電膜を有する基板例え
ばガラス基板(1)上にガリュームを珪素に対し6.1
〜1モルチ添加した反応性気体を反応炉(2)にこの系
を十分真空引をして残留酸素を十分除去した後供給し、
この圧力を0.05〜1torr K L/た。
Thus, on a substrate having a transparent conductive film of tin oxide (to which 2 to 10 parts of antimony oxide has been added) on a substrate, for example, a glass substrate (1), gallium is added to 6.1% of silicon.
~1 molt of reactive gas added to the reactor (2) is supplied after the system is sufficiently evacuated to sufficiently remove residual oxygen,
This pressure was 0.05-1 torr KL/.

この後0.1〜lo’OMHz例えば13.56MHr
;の周波数の高周波エネルギを(6)よシミ極鱈(4)
に供給してプラズマ反応をおこさせた。
After this, 0.1~lo'OMHz e.g. 13.56MHr
The high frequency energy of the frequency of (6) and the stain polar cod (4)
was supplied to cause a plasma reaction.

この電気エネルギを供給するタイムチャートの一列を第
3図に示す。
A sequence of time charts for supplying this electrical energy is shown in FIG.

第3図(4)は補助回路がない場合のタイムチャートで
ある電気エネルギの供給(ハ)マツチング点をさがす(
財)マツチング状態移動する過渡状態(ハ)最適出力の
調整中(30)M出方にてPCVDを実施中(3])で
ある。
Figure 3 (4) is a time chart when there is no auxiliary circuit. Electrical energy supply (c) Searching for matching point (c)
(3) A transient state in which the matching state moves (3) The optimum output is being adjusted (30) PCVD is being performed on the M output (3).

この第3−皐(4)において入射出方に)反射出力(ハ
)の差が反応性気体に加えられた出方である。図面よシ
明らかな如(、PCVD中の出方(ハ)に比べて初期状
態(31)はきわめて高く、さらに過渡状態(ハ)(3
0)Kても被形成面をスパッタリングしてしまっていた
。このため導電性電極上にこのP型半導体層を50〜1
50Aときわめて薄い厚さにて均質に電極と何ら損傷を
与えずに作ることは不可能であった。
In this third line (4), the difference in reflected output (c) between the input and output directions is the output direction added to the reactive gas. As is clear from the drawing, the initial state (31) is extremely high compared to the appearance during PCVD (c), and the transient state (c) (3
0) Even with K, sputtering occurred on the surface to be formed. For this reason, this P-type semiconductor layer is placed on the conductive electrode at 50 to 1
It was impossible to make the electrode uniformly at an extremely thin thickness of 50A without causing any damage to the electrode.

第3図(B)はこのための第2図に示す本発明の補助回
路を加えた場合である。
FIG. 3(B) shows the case where the auxiliary circuit of the present invention shown in FIG. 2 for this purpose is added.

この補助回路をつけたため、初期放電も(A)の22W
より 3Wで成就することができ、このため被形成面に
全く損傷を与えないことがわかった。
Because this auxiliary circuit was installed, the initial discharge was also 22W (A).
It has been found that this can be achieved with just 3W, and therefore does not cause any damage to the surface on which it is formed.

さらにこノ(B)Kテ初期放電(31)、 (32)は
POVD中の主放電(ハ)に比べて同じかまたは弱くす
ることができるため、放電開始に必要な電圧が小さく、
そのため放電開始時に反応性気体に基板を損傷しやすい
強い運動エネルギを与えることがなかった。
Furthermore, since the initial discharges (31) and (32) can be made the same or weaker than the main discharge (c) during POVD, the voltage required to start the discharge is small.
Therefore, at the start of discharge, strong kinetic energy that would easily damage the substrate was not imparted to the reactive gas.

これは第2図に示す如き補助回路にて強いプラズマを誘
発し、この強いプラズマを主電極方向に拡げることによ
シ、放電開始に必要な主電極(3)、(4)での電圧を
下げたことによる。
This is done by inducing strong plasma in an auxiliary circuit as shown in Figure 2, and by spreading this strong plasma toward the main electrodes, the voltage at the main electrodes (3) and (4) required to start the discharge is reduced. Due to lowering it.

かくして第2図においてP型半導体層を作製した。この
後この反応炉または他の反応炉にて丁型の非単結晶珪素
半導体層とP型半導体層を作ると同様の工程にて0.3
〜0.6μの厚さに形成した。本発明の補助回路を用い
ると、この丁型半導体層を形成するに際しても、その下
の被形成面を構成するP型半導体層をスパッタすること
がなく、そのためこのP型半導体層よシ■価の不純物の
丁型半導体層へのオートドーピングによる混入をきわめ
て少なくおさえることができた。
In this way, a P-type semiconductor layer as shown in FIG. 2 was fabricated. After that, if a D-shaped non-single crystal silicon semiconductor layer and a P-type semiconductor layer are made in this reactor or another reactor, 0.3
It was formed to a thickness of ~0.6μ. When the auxiliary circuit of the present invention is used, even when forming this D-type semiconductor layer, there is no sputtering of the P-type semiconductor layer constituting the surface to be formed underneath, and therefore the P-type semiconductor layer has a high The incorporation of impurities into the D-type semiconductor layer by autodoping could be suppressed to an extremely low level.

すなわち従来方法で■価の不純物をホウ素とすると、1
〜3X10cm’の不純物の混入があシ、これを本発明
方法を用いると2〜5X10cmにまで下げることがで
きた。また前記した■価の不純物としてガリュームを用
いた本発明方法においては、水素による吸出し効果が々
いため、0.3〜1X10Qm Kまで下げることがで
きた。
In other words, if boron is used as the ■-valent impurity in the conventional method, 1
There was an impurity contamination of ~3×10 cm′, which could be reduced to 2−5×10 cm using the method of the present invention. In addition, in the method of the present invention using gallium as the above-mentioned impurity with a valence of 2, the hydrogen content could be lowered to 0.3 to 1×10 Qm K due to the strong suction effect of hydrogen.

さらに丁型半導体層をかかる低出力で形成し加えてこの
反応性気体の流れの方向に放電室f〜を配し、また被形
成面をもその方向に図示した如くそって設けたことも本
発明を有効にしている0 これは基板を電界に垂直にすると形成された被膜の膜厚
を各基板ごとに不均一になり、また反応性気体が被形成
面に垂直にあたるため、同時にスパッタリングをしてし
まっている。
Furthermore, it is also true that the D-shaped semiconductor layer is formed at such a low power, and the discharge chamber f~ is arranged in the direction of the flow of this reactive gas, and the surface to be formed is also arranged along that direction as shown in the figure. This makes the invention effective.0 This is because if the substrates are placed perpendicular to the electric field, the thickness of the formed film will be non-uniform on each substrate, and the reactive gas will hit perpendicularly to the surface to be formed, making it difficult to perform sputtering at the same time. It's gone.

すなわち本発明のプラズマ反応装置においては、■初期
放電を十分低くして被形成面上のスパッタ効果をなくす
、■被形成面にそって電界が加わシ、反応性気体がその
表面にそって流れるようにしてやはりスパッタ効果をな
くす、■初期放電を主放電よシも低くして、そこでマツ
チングをとることにより、過渡状態における基板への損
傷を少なくする、といったそのすべてを」葡することが
1台角な界面を有する電極−P型半導体層、P型半導体
層−丁型半導体層さらに工型半導体層−N型半導体層を
作る重要な事柄である。
That is, in the plasma reactor of the present invention, (1) the initial discharge is sufficiently low to eliminate the sputtering effect on the surface to be formed, (2) an electric field is applied along the surface to be formed, and reactive gas flows along the surface. In this way, the sputtering effect can be eliminated, and by making the initial discharge lower than the main discharge and matching there, damage to the substrate during transient conditions can be reduced. This is an important matter for forming an electrode-P-type semiconductor layer, a P-type semiconductor layer-Double-type semiconductor layer, and a square-type semiconductor layer-N-type semiconductor layer, each having a trapezoidal interface.

本発明において形成する反応性気体は珪素の非単結晶半
導体を用いた。しかしこれはメタンとシランとを混合し
て作るS i x C1−J (0< xz 1)、シ
ランとアンモニアとの反応によるSi、N、、(0<X
/4)等の異種材料または異種材料の積層においても同
様に有効である。
As the reactive gas formed in the present invention, a non-single crystal semiconductor of silicon was used. However, this is due to Si x C1-J (0<xz 1) made by mixing methane and silane, Si, N, (0<
It is also effective in the case of different materials such as /4) or lamination of different materials.

また形成される材料がアモルファスまたは5〜100A
の2119性を有するセミアモルファス半導体また被形
成面上に繊維構造を有する成長性をも具備する非単結晶
半導体においても有効である0 第2図の実施例は筒状の反応炉の1基のみである。しか
しこれを複数個例えばP1工、N型半導体層をそれぞれ
独立に作るために連結して設けてもよい。この場合には
本発明人の出願になる特許願 半導体装置製造装置(5
6−19z292゜192293 S56.11.30
)に示されている。本発明はかかるプラズマOVD 装
置にもそのまま適用できることはいうまでもない0 実施例2 第4図は本発明の他の構造を示すものである。
Also, the material formed is amorphous or 5~100A
It is also effective for semi-amorphous semiconductors that have the properties of It is. However, a plurality of these layers may be connected to each other in order to independently form a P1 layer and an N-type semiconductor layer. In this case, the patent application to be filed by the inventor: Semiconductor device manufacturing equipment (5)
6-19z292゜192293 S56.11.30
) is shown. It goes without saying that the present invention can be applied as is to such a plasma OVD apparatus.Embodiment 2 FIG. 4 shows another structure of the present invention.

この反応炉は反応性気体が導入口(8)より一方の電極
をかねた噴出口よυ下方向に放出され、一対を構成する
電極(3)、(4)との間にプラズマ放電を行なわしめ
ようとするものである。基板の加熱は図面では他の電極
(4)にてヒーター(7)、電極α力によシ成就してい
る。補助回路(5)はこの場合反応炉中に設けられ、実
施例1の如き反応炉の外側に配置された場合と同様の効
果を有していた。高周波エネルギは(6)よシ一対をな
す電極(3)(4)に供給されている。反応生成物の排
出(9)はロータリーポンプ00)Kよシなされる。本
発明において電極(3)はその電極とステンレス製反応
炉との間で寄生放電がおきないように、セラミックj (社)をはさんでHaに)でおおっている。被形成面を
有する基板は、この場合熱の伝導のため電極(4)上に
配置した。この加熱は赤外線ランプを用いたふく耐力式
の4J 、、、第3図と同様に反応炉の流れに平行に垂
直に林立させることができる。
In this reactor, reactive gas is emitted downward from an inlet (8) through a spout that serves as one electrode, and a plasma discharge is generated between the pair of electrodes (3) and (4). It is an attempt to close the gap. In the drawing, heating of the substrate is accomplished by a heater (7) and electrode α force at another electrode (4). The auxiliary circuit (5) was in this case placed inside the reactor and had the same effect as when placed outside the reactor as in Example 1. High frequency energy is supplied to a pair of electrodes (3) and (4) across (6). The reaction product is discharged (9) by a rotary pump 00)K. In the present invention, the electrode (3) is covered with a ceramic material (Ha) in order to prevent parasitic discharge between the electrode and the stainless steel reactor. The substrate with the surface to be formed was in this case placed on the electrode (4) for heat conduction. This heating can be carried out in parallel to and perpendicular to the flow of the reactor, as in the case of 4J, which uses an infrared lamp, as shown in Fig. 3.

いずれにおいても、この実施例においても補助回路(5
)を設けることにより、初期放電を主放電に比べて同じ
く低くすることができ、またマツチングのずれに対する
同調も低出力状態の時打なわせることができた。
In any case, in this embodiment as well, the auxiliary circuit (5
), it was possible to make the initial discharge similarly lower than the main discharge, and it was also possible to synchronize against mismatching in a low output state.

このため被形成面でのプラズマ放電の問題に関する損傷
を従来に比べてほとんど除去することができた。
Therefore, damage caused by plasma discharge on the surface to be formed can be almost completely eliminated compared to the conventional method.

以上の説明よシ明らかな如く、本発明は容量結合型のプ
ラズマ反応において、1〜20Wの低い出力にて放電を
させようとする時、放電を開始するために15〜56W
の高い放電をさせることによシ被形成面に損傷を与える
ことなく、2τ電極間を導線または5〜xoofLの抵
抗性導線にて電気配線で1屹する程度で成就することが
でき、その工業的効果の大きさに比べてきわめて簡単に
プラズマCvDで形成される被膜の特性のをすることが
できた。
As is clear from the above explanation, in a capacitively coupled plasma reaction, when attempting to cause a discharge at a low output of 1 to 20 W, the present invention is capable of using 15 to 56 W to start the discharge.
By generating a high discharge, it is possible to achieve this without damaging the surface on which it is formed, with just one electric wire between the 2τ electrodes or a resistive conductor wire of 5 to xoofL, and the industry is The characteristics of the film formed by plasma CVD could be determined very easily compared to the magnitude of the effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を実施するための等価回路を示す0 第2図は本発明を用いて作られたプラズマ0VD装置の
概要を示す0 第3図は従来および本発明の反応装置におけ流側を示す
。 1 船2閃 −196一 時間(4力→ !3聞
Fig. 1 shows an equivalent circuit for carrying out the present invention. Fig. 2 shows an outline of a plasma 0VD device made using the present invention. Fig. 3 shows a flowchart in the conventional and inventive reactors. Show the side. 1 Ship 2 Sen - 196 1 hour (4 powers → ! 3 hearings

Claims (1)

【特許請求の範囲】 1、 プラズマ気相反応炉内を反応性気体で充填して所
定の圧力とする工程と、プラズマ気相反応を行なわせる
電気エネルギよりも低い電気エネルギを容量性放電電極
に供給する工程と、この電気エネルギを与えつつその電
極間のインピーダンスの同調をとる工程と、プラズマ気
相反応を行なう所定の電気エネルギを供給する工程とを
有することを特徴とするプラズマ気相反応方法。 2、特許請求の範囲第1項において、低い電気エネルギ
を供給してYツチングをとることによシ、補助回路部に
プラズマ放電を実施せしめることを特徴とするプラズマ
気相反応方法。
[Claims] 1. Filling the inside of a plasma gas phase reactor with a reactive gas to a predetermined pressure, and supplying a capacitive discharge electrode with electrical energy lower than the electrical energy that causes the plasma vapor phase reaction. A plasma vapor phase reaction method characterized by comprising a step of supplying electric energy, a step of tuning the impedance between the electrodes while applying this electric energy, and a step of supplying a predetermined electric energy for performing a plasma gas phase reaction. . 2. A plasma vapor phase reaction method according to claim 1, characterized in that the auxiliary circuit section is caused to perform plasma discharge by supplying low electrical energy to take Y-tching.
JP4783282A 1982-03-25 1982-03-25 Plasma gas phase reaction method Granted JPS58163434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4783282A JPS58163434A (en) 1982-03-25 1982-03-25 Plasma gas phase reaction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4783282A JPS58163434A (en) 1982-03-25 1982-03-25 Plasma gas phase reaction method

Publications (2)

Publication Number Publication Date
JPS58163434A true JPS58163434A (en) 1983-09-28
JPS634449B2 JPS634449B2 (en) 1988-01-29

Family

ID=12786324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4783282A Granted JPS58163434A (en) 1982-03-25 1982-03-25 Plasma gas phase reaction method

Country Status (1)

Country Link
JP (1) JPS58163434A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116125A (en) * 1983-11-29 1985-06-22 Zenko Hirose Film forming method
JPS63246829A (en) * 1986-12-19 1988-10-13 アプライド マテリアルズインコーポレーテッド Application and on-site multistage planaring process for hot cvd/pecvd reactor and thermochemically evaporation of silicon oxide

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116125A (en) * 1983-11-29 1985-06-22 Zenko Hirose Film forming method
JPH0523050B2 (en) * 1983-11-29 1993-03-31 Zenko Hirose
JPS63246829A (en) * 1986-12-19 1988-10-13 アプライド マテリアルズインコーポレーテッド Application and on-site multistage planaring process for hot cvd/pecvd reactor and thermochemically evaporation of silicon oxide
JPH0612771B2 (en) * 1986-12-19 1994-02-16 アプライド マテリアルズインコーポレーテッド TEOS plasma CVD method
US6167834B1 (en) 1986-12-19 2001-01-02 Applied Materials, Inc. Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process

Also Published As

Publication number Publication date
JPS634449B2 (en) 1988-01-29

Similar Documents

Publication Publication Date Title
TWI228786B (en) Electrostatic chucking stage and substrate processing apparatus
KR101952982B1 (en) Method for manufacturing composite wafers
TW200830942A (en) Contamination reducing liner for inductively coupled chamber
TW200308044A (en) Electrostatic chucking stage and substrate processing apparatus
JP2616760B2 (en) Plasma gas phase reactor
JPS58163434A (en) Plasma gas phase reaction method
US20070155132A1 (en) Method of manufacture for a component including at least one single-crystal layer on a substrate
US11410869B1 (en) Electrostatic chuck with differentiated ceramics
JPS6044970B2 (en) Plasma reaction equipment
JPWO2009057185A1 (en) CVD equipment
JPH05306462A (en) Plasma cvd apparatus
JPH05136111A (en) Pre-treatment method of semiconductor device and device with its function
JP2002324760A (en) Film forming method
JPH0544017A (en) Formation of silicon nitride film
JP2008276984A (en) Plasma processing device and dielectric window
JPH08195348A (en) Semiconductor device manufacturing equipment
JP6433502B2 (en) Plasma reaction vessel and assembly and method for performing plasma treatment
JPS58163435A (en) Apparatus for plasma reaction
JP4355490B2 (en) Deposited film forming equipment
JP2008244389A (en) Vacuum treatment apparatus, vacuum treatment method, and plasma cvd method
KR20180064618A (en) Method for Deposition of Thin Film
JP3073675B2 (en) Tray for semiconductor thin film manufacturing equipment
JPH05144754A (en) Film forming apparatus
JP2918194B2 (en) Plasma processing apparatus and plasma processing method
AU2007202645A1 (en) Method of manufacture for a component including at least one single-cyrstal layer on a substrate