JPS5815333A - Counting system - Google Patents

Abstract

PURPOSE:To remarkably improve the counting speed of input information, by repeating the addition of the same digits until output signals of the same digits become equal with a binary one-digit full adder, and forming binary coded information through the arrangement of remained digits. CONSTITUTION:With an inputted number of 7 in decimal number, 2<0> digit signals 201-207 go to logical 1 and a signal 208 goes to 1 with an information storage register set signal 501. A 2<0> digit signal 322 of the output of full adders 31-33 goes to logical 1, signals 312 and 322 go to logical 0 and 2<1> digit signals 311, 321 and 331 go to logical 1. A 2<0> digit signal 352 of the output of full adders 34 and 35 goes to logical 1, a 2<1> signal 351 goes to logical 0, a signal 342 to logical 1, and a 2<2> digit signal 341 goes to logical 1. An output 2<1> digit signal 362 of a full adder 36 goes to logical 1, and a 2<2> digit signal 361 goes to logical 0. A 2<2> digit signal 372 of an output of a full adder 37 goes to logical 1 and 2<2> digit signal goes to logical 0. To an output register 40, 0111 in binary code is set with a register setting signal 502 and applied to an upper-order device 60.

Description

【発明の詳細な説明】 本発明は計数方式、特に一般的な計算機を含む情報処理
装置に適用し、複数の情報源からの入力情報を計数する
計数方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counting method, and particularly to a counting method that is applied to an information processing device including a general computer and counts input information from a plurality of information sources.

従来、情報処理装置における複数の情報源からの人力情
報（論理１又扛０）の計数装置に於いては、入力情報を
情報源の数だけの桁数を持ったシフトレジスタで並列に
受信したのち、その桁数だけシフトさせ、該出力？：２
進力９ンタで計数することにより情報量を計数していた
。従って、情報源の数に応じた桁数のシフトレジスタが
必要で。Conventionally, in a counting device for manually inputting information (logical 1 or 0) from multiple information sources in an information processing device, input information is received in parallel by a shift register having as many digits as the number of information sources. After that, shift by that number of digits and output the corresponding output? :2
The amount of information was counted by counting with a Shinryoku 9-meter. Therefore, a shift register with a number of digits corresponding to the number of information sources is required.

該桁数だけシフトするための時間を必要とした。It took time to shift by the number of digits.

本発明の目的は、従来のもののこのような欠点を除去し
複数の情報源からの情報を、情報源の数に応じた複数の
２進１桁全加算器を設け１回路接続を２進化符号となる
ように構成することにより、２進１桁全加算器の接続段
数分の合計遅延時間内で高速に計数することが可能とな
る計数方式を提供することにある。The purpose of the present invention is to eliminate such drawbacks of the conventional ones and convert information from a plurality of information sources into a binary code by providing a plurality of binary one-digit full adders corresponding to the number of information sources. It is an object of the present invention to provide a counting method which makes it possible to perform high-speed counting within the total delay time corresponding to the number of connected stages of binary one-digit full adders.

本発明によれば情報源の数に応じた第１群の２進１桁全
加算器と、該第１＃の全加算器の夫々の同一桁の出力信
号を入力信号とする第２群の２進１桁全加算器とを含み
、同一桁の出力信号が一つになるまで、同一桁の加算を
繰返し、残った各々の桁の信号より２進符号化の情報を
作成することｔ−特徴とする計数方式が得られる０ 次に本発明の実施例について図を参照して説明する。According to the present invention, a first group of binary one-digit full adders corresponding to the number of information sources and a second group of binary one-digit full adders whose input signals are output signals of the same digit of each of the first # full adders. It includes a binary one-digit full adder, repeats addition of the same digit until the output signal of the same digit becomes one, and creates binary encoded information from the signal of each remaining digit. Next, embodiments of the present invention will be described with reference to the drawings.

第１図は２進１桁全加算器の３つの入力Ｃｎ、Ｂ及びＡ
と和出力Σ９桁上げ出方Ｃｎ＋ｘの２つの出力を表わし
たブロック図で、３つの入力Ｃｎ、Ｂ及びＡの各状態に
対して和出力２１桁上げ出方Ｃｎ＋ｘがどのように変化
するかを表わしたのが第１表で第１表 第２図は本発明の一実施例のブロック図で図において、
２進情報発生装置１１〜１８の？桁値号１０１〜１０８
は制御信号発生回路５０の情報保持レジスタセット信号
５０１により情報保持レジスタ２゜にセットされる。Figure 1 shows the three inputs Cn, B and A of a binary 1-digit full adder.
This is a block diagram showing two outputs, sum output Σ9 carry output Cn+x, and how the sum output 21 carry output Cn+x changes for each state of three inputs Cn, B, and A. This is shown in Table 1, and Table 1 and Figure 2 are block diagrams of one embodiment of the present invention.
Binary information generators 11-18? Digit number 101-108
is set in the information holding register 2° by the information holding register set signal 501 of the control signal generating circuit 50.

うち、を桁信号３１２，３２２及び３３２は全加算器３
５に入力され、該全加算機３５の出力を桁信号３５２が
出力レジスタ４０に入力される。Among them, the digit signals 312, 322 and 332 are sent to the full adder 3.
5, and the output of the full adder 35 is input as a digit signal 352 to the output register 40.

全加算器３１〜３３のもう一方の出力　２１１信号３１
１．３２１及び３３１は、全加算器３４に入力され、該
全加算機３４の出力１桁値号３４２と全加算器３５のも
う一方の出力　２１１信号３５１は全加算器３６に入力
されて該全加算機３６の出力２桁値号３６２は出力レジ
スタ４０に入力される。The other output of full adders 31 to 33 211 signal 31
1.321 and 331 are input to the full adder 34, and the output one-digit value number 342 of the full adder 34 and the other output 211 signal 351 of the full adder 35 are input to the full adder 36 and the The output two-digit value number 362 of the full adder 36 is input to the output register 40.

全加算器３４と３６のもう一方の出力　ｆ桁値号３４１
と３６１は全加算器３７に入力され、該全加算機３７の
出力？桁値号３７２とｔ桁値号３７１は出力レジスタ４
０に入力される。The other output of full adders 34 and 36 f digit value number 341
and 361 are input to the full adder 37, and the output of the full adder 37 is ? Digit value number 372 and t digit value number 371 are output register 4
It is input to 0.

出力レジスタ４０に入力された２’−２”桁信号は出力
レジスタセット信号５０２によシセットされ、該出力レ
ジスタ４０の出力　２’−２”桁信号は上位装置６０に
供給される。The 2'-2'' digit signal input to the output register 40 is set by the output register set signal 502, and the 2'-2'' digit signal output from the output register 40 is supplied to the host device 60.

次に本方式の動作を具体例に従って説明する。Next, the operation of this method will be explained according to a specific example.

２進情報発生装置１１〜１８の出力ｆ桁値号１０１〜１
０７が論理１％同１０８が論理０であったとする。つま
り％１０進数で７の入力数があった場合の動作１例につ
いて説明する。Output f digit value numbers 101 to 1 of binary information generators 11 to 18
Assume that 07 is logic 1% and 108 is logic 0. In other words, an example of the operation when there is an input number of 7 in decimal number will be explained.

情報保持レジスタセット信号５０１によりを桁信号１０
１〜１０８が情報保持レジスタ２０にセットされ、該レ
ジスタの出力　を桁信号２０１〜２０７が論理ｌ、同２
０８が論理０となる。The digit signal 10 is set by the information holding register set signal 501.
1 to 108 are set in the information holding register 20, and the digit signals 201 to 207 are set to logic 1 and 2 to the output of the register.
08 becomes logic 0.

次に、全加算器３１〜３３の出力　を桁信号３２２は論
理１．同３１２及び３３２は論理０とな夛、２ｍ１信号
３１１，３２１及び３３１は論理ｌとなる。Next, the digit signal 322 outputs the outputs of the full adders 31 to 33 as logic 1. The signals 312 and 332 are logic 0, and the 2m1 signals 311, 321, and 331 are logic 1.

次に、全加算器３４及び３５の出力　を桁信号３５２は
論理１．２１１信号３５１は論理Ｏ１同３４２は論理１
％を桁信号３４１は論理ｌとなる。Next, the outputs of the full adders 34 and 35 are as follows: The digit signal 352 is logic 1.211, the signal 351 is logic O1, and the digit signal 342 is logic 1.
The % digit signal 341 becomes logic l.

次に、全加算器３６の出力２ｍ１信号３６２は論理１と
なり、２２２信号３６１は論理０となる。Next, the output 2m1 signal 362 of the full adder 36 becomes a logic 1, and the 222 signal 361 becomes a logic 0.

次に、全加算器３７の出力　２桁値号３７２Ｆｉ論理ｌ
となり、を桁信号３７１は論理０となる。Next, the output of the full adder 37 2-digit value number 372Fi logic l
Therefore, the digit signal 371 becomes logic 0.

従って、出力レジスタ４０には出力レジスタセット信号
５０２によル２進化符号の０１１１　（１０進数の７を
意味する）がセットされ、該出力４０１が上位装置６０
に供給される。Therefore, the binary code 0111 (meaning 7 in decimal) is set in the output register 40 by the output register set signal 502, and the output 401 is sent to the host device 60.
supplied to

本発明は以上に説明したように、２進１桁全加算器によ
シ同−桁の出力信号が一つになる迄、同一桁の加算を繰
返し、残った６夕の桁を並べ２進符号化の情報を作成す
ることによ多入力情報の計数速度を大幅に改善する効果
がある０As explained above, the present invention uses a binary one-digit full adder to repeat the addition of the same digit until the output signal of the same digit becomes one, and then arranges the remaining six digits and converts them into binary Creating encoded information has the effect of greatly improving the counting speed of multiple input information0

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は２進１桁全加算器の一例のブロック図、第２図
は本発明による計数方式の一実施例の構成を示すプロ゛
ツク図である。 １１〜１８・・・・・・２進情報発生装置、２０・・・
・・・情報保持レジスタ回路、３１〜３７・・・・−・
２進１桁全加算器、４０−・・・・出力レジスタ回路、
５０・・・・・・制御信号発生回路、６０・・・・・・
上位装置、１０１〜１０８゜２０１〜２０８，３１２，
３２２，３３２，３５２・・・・・・を桁信号、３１１
，３２１，３３１，３４２，３５１，３６２・・・・・
・・２１１信号、３４１，３６１，３７２・・・・・・
ｆ桁値号、３７１−−−−−２”桁信号、４０１・・・
・・・２’−２”桁信号、５０１・・・・・・情報保持
レジスタセット信号、５０２・・・・・・出力レジスタ
セット信号、１００１−１００３・・・・・・論理０信
号。 第　ｌ　図FIG. 1 is a block diagram of an example of a binary one-digit full adder, and FIG. 2 is a block diagram showing the configuration of an embodiment of the counting system according to the present invention. 11-18...Binary information generator, 20...
...Information holding register circuit, 31-37...-
Binary 1-digit full adder, 40-...output register circuit,
50... Control signal generation circuit, 60...
Upper device, 101~108°201~208,312,
322, 332, 352... is the digit signal, 311
,321,331,342,351,362...
・211 signal, 341, 361, 372...
f digit value number, 371---2'' digit signal, 401...
...2'-2'' digit signal, 501... Information holding register set signal, 502... Output register set signal, 1001-1003... Logical 0 signal. l figure

Claims (1)

【特許請求の範囲】[Claims] 情報源の数に厄じた第１群の２進１桁全加算器と、該第
１群の全加算器の夫々の同一桁の出力信号を入力信号と
する第２群の２進１桁全〃口算器とを含み、同一桁の出
力信号が一つになるまで、同一桁の加算を繰返し、残っ
た各々の桁の信号より２進符号化の情報を作成すること
を特徴とする計数方式。A first group of binary 1-digit full adders due to the number of information sources, and a second group of binary 1-digit full adders whose input signals are the same-digit output signals of the first group of full adders. A counting machine that includes a total counter, repeats addition of the same digit until the output signal of the same digit becomes one, and creates binary encoded information from the signal of each remaining digit. method.