JPS58143551A - Wiring method for semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need for the formation of a contact hole, and to prevent the disconnection of upper-layer wiring by changing the surface of lower-layer wiring obtained by selecting regions crossing with upper-layer wiring into an insulating film and forming upper-layer wiring. CONSTITUTION:An insulating layer is etched selectively at first while using a resist pattern 11 with a pattern reverse to a wiring pattern in a substrate 10, to which the insulating layer is formed, as a mask, and an insulating-layer pattern 13 is obtained. A metal as lower-layer wiring is deposited so as to form film thikness approximately the same as the insulating film while using said resist and the insulating film as spacers, and lower-layer wiring 12 is formed through a lift-off method. Only a region 16, in which insulating property must be kept electrically to upper-layer wiring, is exposed selectively, approximately half the film thickness of lower-layer wiring is anodic-oxidized from the surface while employing the resist as a mask, and an insulating layer 15 is formed into a region, in which electric insulating property must be kept, among crossing regions. The resist used as the mask of anodic oxidation is removed, a resist film 17 is formed newly, and upper-layer wiring 16 is shaped through a lift-off method while using the resist film as a spacer.

Description

【発明の詳細な説明】 〔＠明の楓する技術分野〕 本発明は多層配線を有する半導体装置の配線方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [@Mei's Technical Field] The present invention relates to a wiring method for a semiconductor device having multilayer wiring.

〔従来技術とその問題点〕[Prior art and its problems]

従来、多層配線を形成する方法として、例えば第１図に
示す如く、下層配ｆｓ２を絶縁［３で覆い絶縁膜、３に
コンタクトホール２ａを形成し、その伏上層配置＃！４
ｔ−形成するものが知られている。Conventionally, as a method for forming multilayer wiring, for example, as shown in FIG. 1, the lower layer fs2 is covered with an insulating film [3], a contact hole 2a is formed in the insulating film 3, and the upper layer is arranged #! 4
Those that form t- are known.

しかしながら、これＫよるとコンタクト・ホール２ａを
配置２に正確に位置合せして形成したけれはならないこ
と、またエツチング精度を出し難いこと、更に★九５で
示し九カバレージの悪さにより配線４が断線し中すいこ
となどの問題がある。However, according to K, it is necessary to form the contact hole 2a accurately aligned with the arrangement 2, and it is difficult to achieve etching accuracy.Furthermore, the wiring 4 may be disconnected due to poor coverage as indicated by ★95. There are problems such as the lack of water.

〔発明の目的〕[Purpose of the invention]

本発明は多層配線を形成する際に、配線層間を結ぶコン
タクトホールを形成せずに済み、また段差に起因する上
層配線の断線が起らないようにする領域方法を提供する
ことを目的とする。An object of the present invention is to provide an area method that eliminates the need to form contact holes between wiring layers and prevents disconnection of upper layer wiring due to steps when forming multilayer wiring. .

〔発明の概要〕[Summary of the invention]

本発明は下層配線を設ける工程と、少くとも上層配線と
交差する領域のうちから選択して得た下層配線表面を絶
縁膜に変換する工程と、上層配線を設ける工程とを含む
ことを特徴とする半導体装置の配線方法である。The present invention is characterized in that it includes a step of providing a lower layer wiring, a step of converting the surface of the lower layer wiring obtained by selecting at least a region intersecting with the upper layer wiring into an insulating film, and a step of providing the upper layer wiring. This is a wiring method for semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

この発明により、段差に起因する断巌等を生じることな
く、多層配線を高精度かつ容易に形成できる。According to the present invention, multilayer wiring can be easily formed with high precision without causing cracks or the like due to differences in level.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面を用いて旺細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第２図−）は本発明の一夾施例を示す平面図、第２図（
ｂ）ないしくｇ）は工程順に示した（ａ）図０Ｂ−Ｂで
の断面図である。Figure 2-) is a plan view showing one embodiment of the present invention;
b) to g) are cross-sectional views taken along line (a) FIG. 0B-B shown in the order of steps.

先ず第２図（ｂ）　Ｋ示すように絶縁層を形成した基板
１０に配線パターンと逆のパターンを有するレジストパ
ターン１１を形成し、このレジストをマスクとして先ず
絶縁層を選択的にエツチングして絶縁層パターン１３を
得る。この際絶縁層のエツチングには、絶縁層が酸化シ
リコン（８ｉ０．）膜なら四弗化縦木−（ＣＦ４　）と
水素（Ｈｍ）の混合ガスを絶−鳩が値化シリコ：／、績
（Ｓ　１ｓＮａ　）ならＣＦ、ガスを用いる反応性イオ
ー・エツチング法を適用する。First, as shown in FIG. 2(b) K, a resist pattern 11 having a pattern opposite to the wiring pattern is formed on a substrate 10 on which an insulating layer has been formed, and using this resist as a mask, the insulating layer is first selectively etched to form an insulating layer. A layer pattern 13 is obtained. At this time, when etching the insulating layer, if the insulating layer is a silicon oxide (8i0.) film, a mixed gas of tetrafluoride vertical wood (CF4) and hydrogen (Hm) must be used. S 1sNa ), a reactive sulfur etching method using CF gas is applied.

次に前記レジスト及び絶縁績をスペーサとして下層配線
となる金属を蒸着又はスパッタ等により絶縁膜とほぼ等
しい膜厚となるように堆積せしめる。レジストを溶解し
、レジスト及びレジスト上の金属層を除去せしめ、すな
わちリフトオフ法により下層配線１２を形成し九ものが
第２図（Ｃ）である、この際、前記下層配線としては陽
極酸化が可能な金属、友とえばＡｊ１チタン又はタンタ
ルなどから選ぶのが遍轟である。Next, using the resist and the insulation film as spacers, a metal that will become the lower wiring is deposited by vapor deposition, sputtering, etc. so that it has approximately the same thickness as the insulation film. The resist is melted and the resist and the metal layer on the resist are removed, that is, the lift-off method is used to form the lower layer wiring 12, as shown in FIG. 2(C). At this time, the lower layer wiring can be anodized. It is a matter of choice to choose from suitable metals such as Aj1 titanium or tantalum.

次に基板上にレジストを形成し、バターニングして、上
層配線と電気的に絶縁性が保たれるべき領域１６のみを
第２図（ｄ）Ｋ示すように選択的に露出し、レジストを
マスタとして下層配線の膜厚の約半分を表面から陽極酸
化する。これにより下層配線のうち、少くと本上層配線
との交差領域のうちで電気的絶縁性を検死れるべき領域
に絶縁層１５が形成されえ（第２図１６）　）　。Next, a resist is formed on the substrate and patterned to selectively expose only the region 16 that should be electrically insulated from the upper layer wiring as shown in FIG. 2(d)K. As a master, approximately half of the film thickness of the lower wiring is anodized from the surface. As a result, the insulating layer 15 can be formed in the lower layer wiring at least in the area where it intersects with the main upper layer wiring and whose electrical insulation should be examined (FIG. 2, 16).

次いで１１２図（ｆ）　Ｋ示すようＫ１１ｌＩ極酸化の
マスクとして用いたレジストを除去した後新たｒ（レジ
ス）［１７を形成する。このレジスト膜１７［ＩＪ配線
パターンと逆のパターンを有するようニ形成する。そし
てとＯレジス）Ｍをスペーサとしてり７トオフ法によ努
上層配Ｍｌ　６を形成する（第２図（Ｊり　）。Next, as shown in FIG. 112(f) K, after removing the resist used as a mask for K11I polar oxidation, a new r (resist) [17 is formed. This resist film 17 is formed so as to have a pattern opposite to the IJ wiring pattern. Then, an upper layer Ml 6 is formed by using the 7-off method using the O-regis) M as a spacer (FIG. 2).

上述の説明で明らかなように５本実施例で得られ走多層
配線構造においては下地表面が平担に形成され石ので、
その上層配線に段差に起因する断線を生じる仁とがなく
、シかも層間絶縁膜は電気的絶縁性が必要な交差領域圧
しが設けられてぃないので、コンタクＦホールの形成が
不要にな夛。As is clear from the above explanation, in the multi-layer wiring structure obtained in the five embodiments, the underlying surface is flat and stone-like;
The upper layer wiring has no grooves that would cause disconnection due to steps, and the interlayer insulating film does not have any cross-area pressure that requires electrical insulation, so there is no need to form contact F holes. .

その位置合せ不要やエツチング精度不要の問題が除かれ
た。This eliminates the need for alignment and etching accuracy.

〔発明の他の実施例〕[Other embodiments of the invention]

上記実施例において下層配線の厚さをスペーサ用絶縁績
１３とはは同一にし九が、必ずしも厳密に一致させる必
ｌＩＩ／Ｉｉなく、２ｏ−程度の範囲で増加又は減少す
ることは許容できる。＊記スベーナ用絶縁編も８１０３
中８４Ｎ４に限らない、また絶縁績のエツチングの方法
及び使用するガス等も絶縁膜Ｏ材質により適宜選択しう
るも〇である。まえ上層配線の形成の方法はリフトオフ
法に、限定されない、更に本発明は、陽ｌ１ＩＩｌ化可
能な金属を順次用いる限り、３層以上の多層配線の形成
に用いて良い、この場合＃ｌ２ＷＪ（ｆＪの代りにｊ１
３Ｆ１！Ｊに示す断面図で説明され為工１を行えばよい
、すなわちリフトオフのスペーサとしてレジス）１７０
代如にレジスト１９及び絶縁１１１３とはエツチング譬
性　′が異な為絶縁属１８０２層スペーサを用いればよ
い、絶縁績１８は適宜選択したガスによル、ドライエツ
チングを行ってパターン形成することができる。In the above embodiment, the thickness of the lower layer wiring is made to be the same as that of the spacer insulation layer 13, but it is not necessarily necessary to make the thickness match exactly, and it is permissible to increase or decrease the thickness within a range of about 2o. *Insulation version for subena is also 8103
The etching method is not limited to 84N4, and the method of etching the insulation and the gas used can be selected as appropriate depending on the material of the insulation film. The method for forming the upper layer wiring is not limited to the lift-off method. Furthermore, the present invention may be used to form a multilayer wiring of three or more layers as long as metals that can be positively converted into l1IIl are sequentially used. In this case, #l2WJ (fJ j1 instead of
3F1! It is sufficient to carry out the construction 1 as explained in the cross-sectional view shown in J, that is, to use the resist as a lift-off spacer) 170
Alternatively, since the resist 19 and the insulation 1113 have different etching tolerances, it is sufficient to use an insulating metal 1802 layer spacer.The insulation 18 can be patterned by dry etching with an appropriately selected gas. .

更に前記実施例においては下層配線の表面のうち上層配
線と交差すゐ領域のうちから選択して陽極酸化を行い配
−関を絶縁し九が、別の方法として交差する領域のすべ
てＫついて陽極酸化を行ってもよい、このｓ％上層配線
と下層配線との間に電気的″＊ａを要する場合には、＃
幽する領域の陽極酸化絶縁層を新九に適轟な手段を用い
て除去すればよい。Further, in the embodiment described above, the area of the surface of the lower layer interconnection that intersects with the upper layer interconnection is selected and anodized to insulate the interconnection. However, in another method, all of the intersecting area K is anodized. Oxidation may be performed. If electrical "*a" is required between this s% upper layer wiring and lower layer wiring, #
The anodic oxidation insulating layer in the area to be removed may be removed using a suitable method.

［Ｋ前述０８実施例においては、交差する配皺のうち選
択しぇ領域について下層配線部表向を犀出するようなレ
ジストマスタを用いて陽極酸化を行つ友が、第［０（ｂ
）の段階で下層配＃ｉ２の表面を１ＩＩＩａｌｌ化して
もよい、この場合には上層配線との電気的接続を要すゐ
領域０みにおいて陽極酸化絶縁膜を除去すゐようにマス
クを設ければよい。[K In the above-mentioned Example 08, the anodic oxidation is carried out using a resist master that exposes the surface of the lower wiring part for selected areas among the intersecting wrinkles.
) The surface of the lower layer wiring #i2 may be made into 1IIIall. In this case, a mask should be provided so that the anodized insulating film is removed only in the area 0 where electrical connection with the upper layer wiring is required. Bye.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例０平画図及び断面図、第２図（ａＪは本
発明における一実施例の平ｌ１ｌＩ図、第２図ｆｂ、ｌ
ないしは）は本発明における一実施例の工程断面図、第
３図は本発明の他の実施例の断面図である。 １０・・・基　板　　　　１１，１４，１７．１９・・
・レジスト１２・・・下層配線　　　１３−・・スペー
サ絶縁膜ｌト・・陽極酸化膜　　１６・・・・上層配線
１８・・・絶縁膜Fig. 1 is a plan view and a sectional view of the conventional example 0, Fig. 2 (aJ is a plan l1lI view of an embodiment of the present invention, Fig. 2 fb, l
1 to 3) are process cross-sectional views of one embodiment of the present invention, and FIG. 3 is a cross-sectional view of another embodiment of the present invention. 10... Board 11, 14, 17. 19...
・Resist 12...Lower layer wiring 13-...Spacer insulating film Lt...Anodized film 16...Upper layer wiring 18...Insulating film

Claims (1)

【特許請求の範囲】[Claims] 下層配線を設ける工程と、少くとも上層配線と交差する
領域のうちから選択した下層配線表面を絶縁−に変換す
る工程と、上層配線を設ける工程とを含むことを％徴と
する半導体装置の配線方法。Wiring for a semiconductor device comprising the steps of providing a lower layer wiring, converting a surface of the lower layer wiring selected from at least a region that intersects with the upper layer wiring into an insulating layer, and providing an upper layer wiring. Method.