JPS58142578A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58142578A JPS58142578A JP57024414A JP2441482A JPS58142578A JP S58142578 A JPS58142578 A JP S58142578A JP 57024414 A JP57024414 A JP 57024414A JP 2441482 A JP2441482 A JP 2441482A JP S58142578 A JPS58142578 A JP S58142578A
- Authority
- JP
- Japan
- Prior art keywords
- clamp
- diode
- resistor
- protection circuit
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、クランプ抵抗及びクランクダイオードからな
る特にゲート保護用の入力保護回路を有する半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having an input protection circuit, particularly for gate protection, consisting of a clamp resistor and a crank diode.
この種の保護回路としては、クランプダイオードがＭＩ
８構造からなるものや、或いは半導体基板中に形成した
ＰＮｇ合ダイオードからなるものが知られている。とこ
ろが、これらのクランプダイオードはすベニ、基板との
間にＰＨ１合を形成する拡散領域を有しているためｋ、
他の箇肩に存在する拡散領域との間にＰＮＰ又はＮＰＮ
ｉｉの寄生トランジスタ構造が生じ、この寄生トランジ
スタが異常入力（ノイズ等）が入ったときに導通してい
わゆ・るラッチアップ現象を引起こし易（なっている。For this type of protection circuit, a clamp diode is
8 structures, or a PNg alloy diode formed in a semiconductor substrate are known. However, since these clamp diodes have a diffusion region that forms a PH1 coupling with the substrate,
PNP or NPN between diffusion regions existing on other shoulders
A parasitic transistor structure (ii) occurs, and this parasitic transistor becomes conductive when an abnormal input (noise, etc.) is input, easily causing a so-called latch-up phenomenon.
この現、象は、入力保護回路の静電破壊強度を大きくす
る程に顕著に生じることが分っている。It has been found that this phenomenon occurs more significantly as the electrostatic breakdown strength of the input protection circuit increases.
本発明は、こうした状況におい１、静電破壊強度を充分
にすると共に、ラッチアップのない信頼性の高い入力保
護回路を提供することを目的とするものである。Under these circumstances, it is an object of the present invention to provide a highly reliable input protection circuit that has sufficient electrostatic breakdown strength and is free from latch-up.
このために本発明によれば、クランプ抵抗及びフラング
ダイオード共に、絶縁層上の半導体膜によって形成する
ととＶ特徴とし、半導体基体とは接合を形成しない構造
によって入力保護回路を構成している。For this reason, according to the present invention, both the clamp resistor and the flang diode are formed of a semiconductor film on an insulating layer, and the input protection circuit is configured with a structure in which no junction is formed with the semiconductor substrate.
以下、本発明の実施例を図面について詳細に説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は、本実施例による入力保護回路を等価的に示す
ものであって、六方端子ＩＮ（ポンディングパッド）と
内部回路素子の儒えば０ＭＯ８用のＭ Ｉ ８ Ｆ Ｅ
Ｔ （Ｍｅｔａｌ Ｉｎ５ｕｌａｔｏｒ ８ｅｍｉｃ
ｏｎ −ｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔ
ｒａｎｓｉｓｔｏｒ） ｌのゲートとの間に１クランプ
抵抗２とクランプダイオード３とが接続されている。ク
ランプダイオード３は、電源ｖｃｃ及びアースとの間に
夫々接続されたＰＮｇ合ダイオード３ｍ、３ｂの組から
なっている。FIG. 1 equivalently shows the input protection circuit according to this embodiment, in which the hexagonal terminal IN (ponding pad) and the internal circuit elements are M I 8 F E for 0MO8.
T (Metal In5ulator 8emic
on -ductor Field Effect T
A clamp resistor 2 and a clamp diode 3 are connected between the gate of the transistor 1 and the gate of the transistor 1. The clamp diode 3 consists of a pair of PNg combination diodes 3m and 3b connected between the power supply VCC and the ground, respectively.
ここで注目すべきことは、上記のクランプ抵抗２及びク
ランプダイオード３が共に、半導体基板４の主面に設け
た８ｉ０．膜５上に形成されたポリ８五膜からなってい
ることである。Ｐ＋脂ポリ８ｉのクランプ抵抗２の一端
はアル１＝ウム配■６Ｉ／ｃよってポンディングパッド
（入力端子）ＩＮｋｌｌ）続され、また他端はアル１＝
ウム配−７によってＭＩ８ＦＢＴ１のゲート及びフラン
グダイオード３鳳、３ｂｋ夫々接続されている。クラン
プダイオード３ｍ、３ｂは、ｐ＋ｉｉｖ＋リ８轟 ８と
Ｎ中型ポリ８ｉ ９とｋよって夫々形成され、オたアル
ミ＋ ｆ）ム装置１１０．１１によって電源ｖ、ｃ及び
アースに夫々導びかれている。なお、図中の１２は層聞
絶″畿属と゛し工のリンガラスである。What should be noted here is that the clamp resistor 2 and clamp diode 3 are both 8i0. It consists of five poly-8 films formed on film 5. One end of the clamp resistor 2 made of P + fat poly 8i is connected to the bonding pad (input terminal) INkll) by the Al1=Um wiring ■6I/c, and the other end is connected to the Al1=
The gate of MI8FBT1 and the flanged diodes 3b and 3b are connected by a wire 7. Clamp diodes 3m, 3b are respectively formed by p+iiv+ri 8 and n medium sized poly 8i 9 and k, and are led to the power supplies v, c and ground, respectively, by aluminum + f) system devices 110.11. . In addition, the number 12 in the figure is a ring glass made from a layerless layer.
このように構成された保護回路によれば、クランプダイ
オード１ｇ、３ｂは互いに逆極性に接続されているので
、入力端子から正、負いずれの異常入力（ノイズ）が入
った場合でもいずれかのダイオード３１又は３ｂが順方
向となり、この順方向電流によってノイズを効果的に吸
収することかでき、充分な静電破壊強度が得られる。し
かも他方のダイオードについては逆方向バイアスされる
から、逆方向耐圧によって破壊に耐えるようｋなってい
る。According to the protection circuit configured in this way, the clamp diodes 1g and 3b are connected with opposite polarities, so that even if either positive or negative abnormal input (noise) is input from the input terminal, either of the diodes will be 31 or 3b is in the forward direction, noise can be effectively absorbed by this forward current, and sufficient electrostatic breakdown strength can be obtained. Moreover, since the other diode is biased in the reverse direction, it is designed to withstand breakdown due to its reverse breakdown voltage.
加えて重畳なことは、クランプ抵抗２及びクランプダイ
オード３共に、基板４とは置台な形成しない絶縁層５上
のポリＳｔ膜からなりているので、既述した如く基板中
の拡散領域との間に寄生トラン夛スタを生じる余地は全
くない。従って、ラッチアップ現象を防止し工素子特性
ｖ！Ｌ好に保持することができる。In addition, since both the clamp resistor 2 and the clamp diode 3 are made of a polyst film on the insulating layer 5 which is not placed on the substrate 4, as mentioned above, there is a gap between the clamp resistor 2 and the clamp diode 3 and the diffusion region in the substrate. There is no room for parasitic transistors to occur. Therefore, the latch-up phenomenon can be prevented and the device characteristics v! It can be held in good condition.
上記の如き回路を製造するｋは通常の半導体技術を適用
すればよい。For manufacturing the circuit as described above, ordinary semiconductor technology may be applied.
例えば第４Ａ図のように、基＠４の主面ＫＬＯ００８（
Ｌｏｃａｌ ０ｘｉｄａｔｉｏｎ ｏｆ ８ｉ１ｉｃｏ
ｎ）技術で８ｉ０．Ｍ５１’形成し、更にそｒ＞上＃ｃ
ＯＶＤＣ化学的気相成長技術）でポＩＪＳｉ膜２０ｔ−
全面に付着させる。このポリ８１膜２０は、ＯＶＤ時の
不純物ガスの供給によってＰ”ｌｔ化された状態で成長
させる。For example, as shown in FIG. 4A, the main surface KLO008(
Local Oxidation of 8i1ico
n) Technology 8i0. M51' is formed, and further above #c
20t-PoIJSi film using OVDC chemical vapor deposition technology
Apply it to the entire surface. This poly 81 film 20 is grown in a P''lt state by supplying impurity gas during OVD.
次に第４Ｂ図のように、ポリ８ｉ膜２０をフォトエツチ
ングでパターニングした後、マスク（例えばフォトレジ
ス））２１ｔ−選択的に彼せ、Ｎ＠不純物（例えはリン
）のイオンビーム２２ｖ照射し、ポリ８ｉ膜の一部ｔ−
Ｎ＋澹ポリ８ｉ ９ｉＣ変換する。これｋよって上述し
たＰＨ１合ななすポリ８ｉクランプダイオード３ｍ、３
ｂｔ’夫々形成することができる。なお、このイオン打
込みは、上記したＭＩ ８ＦｇＴ１のソース又はドレイ
ン領域（Ｎ＋澹領領域１３１４）ｔ’影形成るためのイ
オン打込みと兼ねて行なってもよい。この場合は、ポリ
８Ｍ膜２０の上記パターニングと同時にゲート電極１６
ｖ加工することかで會、続いてこのゲート電極１５’ｔ
’マスクとしエイオンビーム２２ｖ基板４中に打込んで
、Ｎ＋型領領域１３１４ｖ自己整合的に形成することが
できる。Next, as shown in FIG. 4B, after patterning the poly 8i film 20 by photoetching, selectively applying a mask (e.g., photoresist) 21t, ion beam 22V of N@ impurity (e.g., phosphorus) is irradiated. , part of poly8i film t-
Convert N+Poly 8i 9iC. Therefore, the poly 8i clamp diode 3m, 3
bt' can be formed respectively. Note that this ion implantation may also be performed as the ion implantation for forming the source or drain region (N+ region 1314) t' shadow of the MI 8FgT1 described above. In this case, at the same time as the patterning of the poly 8M film 20, the gate electrode 16 is
We then met to process this gate electrode 15't.
'The N+ type region 1314v can be formed in a self-aligned manner by implanting the ion beam 22v into the substrate 4 as a mask.
なおこのイオン打込み後は、リンガラス１２ｔ−ＯＶＤ
で付着せしめ、これをフォトエツチングで加工後に真空
蒸着法でアルミニウムを蒸着し、更にフォトエツチング
でパターニングし１各アルミニウム配＠７．１０．１１
等を形成する。After this ion implantation, phosphorus glass 12t-OVD
After processing this by photoetching, aluminum was deposited by vacuum evaporation method, and then patterned by photoetching to form 1 each aluminum pattern @7.10.11
form etc.
以上、本発明を例示したが、上述の例は本発明の技術的
思想に基いて更に変形が可能である。例えば、上述のポ
リ８１膜は更にレーザーアニール等の手法で単結晶化し
てよい。またポリ８ｉ以外の半導体膜も使用可能である
。上述のクランプダイオードは、ＰＮダイオードのみな
らず、ＰＮＰＮ構造としてよい。本発明はＯＭＯＳ Ｉ
Ｏ等のＩＯやＬ８Ｉｋも適用できる。Although the present invention has been illustrated above, the above-mentioned example can be further modified based on the technical idea of the present invention. For example, the poly 81 film described above may be further made into a single crystal by a method such as laser annealing. Further, semiconductor films other than poly8i can also be used. The above-mentioned clamp diode may have a PNPN structure as well as a PN diode. The present invention is based on OMOS I
IO such as O and L8Ik can also be applied.
図−は本発明の実施例を示すものであっ℃、第１図は入
力保護回路の等価回路図、第２図はその平面図、第３図
は第２図のＸ−Ｘ＠断面図、第４Ａ図及び第４Ｂ図は第
３図の構造の製造ＩＩＣ際する主要工程における各断面
図である。
１・・・内部ＭＯ８，２・・・クランプ抵抗、Ｌ ３
ｍ。
３ｂ・・・クランプダイオード、５・・・８Ｍ０１展、
６゜７．１０．１１・・・アルミニウム配線、８・・・
Ｐ”ｌｌポリＳ１．９・・・Ｎ中型ポリ８１％ ＩＮ−
・・ポンディングパッド。Figure 1 is an equivalent circuit diagram of the input protection circuit, Figure 2 is a plan view thereof, Figure 3 is a sectional view taken along line X-X in Figure 2, and Figure 1 is an equivalent circuit diagram of the input protection circuit. FIGS. 4A and 4B are sectional views of the main steps in manufacturing IIC of the structure shown in FIG. 3. 1... Internal MO8, 2... Clamp resistance, L 3
m. 3b...clamp diode, 5...8M01 exhibition,
6゜7.10.11...Aluminum wiring, 8...
P"ll poly S1.9...N medium poly 81% IN-
...Pounding pad.
Claims (1)
保護回路が構成されている半導体装置において、前記ク
ランプ抵抗及びクランプダイオードが共に、半導体基体
の主面に設けた結縁層上の半導体膜からなっていること
Ｖ＊黴とする半導体装置。1. In a semiconductor device in which an input protection circuit is configured by a clamp resistor and a clamp diode, both the clamp resistor and the clamp diode are made of a semiconductor film on a bonding layer provided on the main surface of a semiconductor substrate.V* Semiconductor devices that become moldy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57024414A JPS58142578A (en) | 1982-02-19 | 1982-02-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57024414A JPS58142578A (en) | 1982-02-19 | 1982-02-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58142578A true JPS58142578A (en) | 1983-08-24 |
Family
ID=12137494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57024414A Pending JPS58142578A (en) | 1982-02-19 | 1982-02-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58142578A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6081871A (en) * | 1983-10-11 | 1985-05-09 | Nec Corp | Vertical field effect transistor and manufacture thereof |
| US4593453A (en) * | 1982-06-01 | 1986-06-10 | Rockwell International Corporation | Two-level transistor structures and method utilizing minimal area therefor |
| JPS63211760A (en) * | 1987-02-27 | 1988-09-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63268265A (en) * | 1987-04-24 | 1988-11-04 | Nec Corp | Semiconductor device |
| WO1990014690A1 (en) * | 1989-05-17 | 1990-11-29 | David Sarnoff Research Center, Inc. | Voltage stress alterable esd protection structure |
| US5010380A (en) * | 1989-05-17 | 1991-04-23 | David Sarnoff Research Center, Inc. | Voltage stress alterable ESD protection structure |
| US5365099A (en) * | 1988-12-02 | 1994-11-15 | Motorola, Inc. | Semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage |
| US20190084375A1 (en) * | 2016-03-10 | 2019-03-21 | Denso Corporation | Air conditioner |
-
1982
- 1982-02-19 JP JP57024414A patent/JPS58142578A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4593453A (en) * | 1982-06-01 | 1986-06-10 | Rockwell International Corporation | Two-level transistor structures and method utilizing minimal area therefor |
| JPS6081871A (en) * | 1983-10-11 | 1985-05-09 | Nec Corp | Vertical field effect transistor and manufacture thereof |
| JPH0516192B2 (en) * | 1983-10-11 | 1993-03-03 | Nippon Electric Co | |
| JPS63211760A (en) * | 1987-02-27 | 1988-09-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63268265A (en) * | 1987-04-24 | 1988-11-04 | Nec Corp | Semiconductor device |
| US5365099A (en) * | 1988-12-02 | 1994-11-15 | Motorola, Inc. | Semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage |
| WO1990014690A1 (en) * | 1989-05-17 | 1990-11-29 | David Sarnoff Research Center, Inc. | Voltage stress alterable esd protection structure |
| US5010380A (en) * | 1989-05-17 | 1991-04-23 | David Sarnoff Research Center, Inc. | Voltage stress alterable ESD protection structure |
| US20190084375A1 (en) * | 2016-03-10 | 2019-03-21 | Denso Corporation | Air conditioner |
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