JPS58142540A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58142540A JPS58142540A JP2624382A JP2624382A JPS58142540A JP S58142540 A JPS58142540 A JP S58142540A JP 2624382 A JP2624382 A JP 2624382A JP 2624382 A JP2624382 A JP 2624382A JP S58142540 A JPS58142540 A JP S58142540A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- aperture
- opening
- bird
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は絶縁分離方式による半導体装置の高密度化高精
度化１歩留同上を図った新規な構造及びその製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure and a method for manufacturing the same, which achieve high density, high precision, and one yield of a semiconductor device using an insulation isolation method.
近年、バイポーラ半導体装置はますます高密度化、高精
度化、高速度化の要求が高まり、従来のｐｎ接合分離方
式から絶縁分離方式へと変更し、集積度を上げる方向に
進んでいる。In recent years, there has been an increasing demand for higher density, higher precision, and higher speed for bipolar semiconductor devices, and the conventional pn junction isolation method has been changed to an insulation isolation method to increase the degree of integration.
絶縁分離方式における一般的な分離方法を第１図ａ、ｂ
に示す。第１図ａにおいて１はたとえばｎ型半導体基板
、２は下地酸化膜、３は酸素を通過しない窒化ケイ素な
どの膜であり１選択酸化におけるマスク材となる。下地
酸化膜２はｎ型半導体基板１と窒化ケイ素膜３の膨張係
数の違いにより、選択酸化時にｎ型半導体基板１に加わ
る応力を緩和するために形成されている。４は窒化ケイ
素膜３、下地酸化膜２を各々エツチングした後、ｎ型半
導体基板１をケミカルエツチングした時に生じたサイド
エッチ部分である。このサイドエッチ量はケミカルエツ
チングが本質的に等方的エッチングなので深さ方向と同
程度、横方向にも生じる。第１図すは第１図ａの後、選
択酸化したときの状態を示している。６は第１図ａの状
態の後選択酸化によって形成された酸化膜であり、６は
選択酸化時に生じた横方向のば化膜いわゆるｂｉｒｃｈ
＋ｂｅａｋと呼ばれるものであり、７も選択酸化時に生
じた突起状の酸化膜いわゆるｂｉｒｄ’ ｓ ｈｅａｄ
と呼ばれるものである。Figure 1 a and b show the general isolation method in the insulation isolation method.
Shown below. In FIG. 1a, 1 is, for example, an n-type semiconductor substrate, 2 is a base oxide film, and 3 is a film made of silicon nitride or the like through which oxygen does not pass, which serves as a mask material in selective oxidation. Base oxide film 2 is formed to relieve stress applied to n-type semiconductor substrate 1 during selective oxidation due to the difference in expansion coefficient between n-type semiconductor substrate 1 and silicon nitride film 3. Reference numeral 4 denotes a side etched portion that is generated when the n-type semiconductor substrate 1 is chemically etched after the silicon nitride film 3 and base oxide film 2 are etched. Since chemical etching is essentially isotropic etching, the amount of side etching occurs in the lateral direction as well as in the depth direction. FIG. 1 shows the state when selective oxidation is performed after FIG. 1a. 6 is an oxide film formed by selective oxidation after the state shown in FIG.
+beak, and 7 is also a protruding oxide film produced during selective oxidation, the so-called bird's head.
It is called.
このｂｉｒｄ’ ｓ ｈｅａｄ 、 ｂｉｒｄ’ ｓ
ｂｅａｋの生じる反応機構は、選択酸化時に供給される
水または酸素が下地酸化＠２を介して横方向にも供給さ
れるためであり、そのためｂｉｒｄ’ｓ ｂｅＩ！ＬＩ
Ｃが生じる。このｂｉｒｄ’ｓ ｂｅａｋ は窒化ケ
イ素膜３とｎ型半導体基板１との間に生じるため、窒化
ケイ素膜３を押し上げるような応力が働き、窒化ケイ素
膜３は持ち上げられるので、いわゆるｂｉｒｄ’ｓｓ
ｈｅａｄ７も生じてくる。ｂｉｒｄ’ｓ ｂｅａｋ ６
が生じると窒化ケイ素＠３が押し上げられるため、水ま
たは酸素の横方向への供給が増し、その結果ｂｉｒｄ’
ｓ ｂｅａｋ 、 ｂｉｒｄ’ｓ ｈｅａｄが大きくな
るという悪循環を繰シ返す。このｂｉｒｄ’ｓ ｂｅａ
ｋ 、 ｂｉｒｄ’ｓ ｈｅａｄの大きさは、我々の実
験によるとたとえば２μｍの酸化膜を形成すると、ｂｉ
ｒｌｓ ｂｅａｋ量１．６ μｍ 、 ｂｉｒｄ’ｓ
ｈｅａｄ １ 、Ｏｐｒｎ 程度となる。このｂｉｒｄ
’ｓ 馳級 は半導体装置の高密度化、高精度化に大き
な障害となる。This bird's head, bird's
The reaction mechanism that causes beak is that water or oxygen supplied during selective oxidation is also supplied laterally via base oxidation @2, and therefore bird's beI! L.I.
C occurs. Since this bird's beak occurs between the silicon nitride film 3 and the n-type semiconductor substrate 1, a stress that pushes up the silicon nitride film 3 acts, and the silicon nitride film 3 is lifted, resulting in the so-called bird's beak.
head7 also appears. bird's beak 6
When this occurs, silicon nitride @3 is pushed up, increasing the lateral supply of water or oxygen, resulting in bird'
The vicious cycle of increasing s beak and bird's head is repeated. This bird's bea
k, the size of the bird's head is, according to our experiments, when an oxide film of 2 μm is formed, bi
rls peak amount 1.6 μm, bird's
They are approximately head 1 and Oprn. this bird
's high quality is a major obstacle to increasing the density and precision of semiconductor devices.
絶縁分離方式によるバイポーラＴｒ（トランジスタ）に
おいては、 Ｔｒ の周囲は分離ば化膜で囲ま扛ている
ため、２μｍの分離酸化膜を形成すると、ｂｉｒｌｓ
ｂｅａｋはＴｒの活性領域を片側からだと１．６μｍ１
両側からだと実に３．２μｍ もつぶすことになり、扁
密度化、高精度化への大きな妨げとなってくる。また、
このｂｉ ｒｄ’ ｓ ｈｅａｋのため、完成したＴｒ
も設計に対して非常に精度の悪いものとなり、集積回路
の特性も悪いものになる。In a bipolar Tr (transistor) using the insulation isolation method, the Tr is surrounded by an isolation oxide film, so if a 2 μm isolation oxide film is formed, the birls
beak is 1.6μm from one side of the active region of the Tr
If viewed from both sides, it would actually be crushed by 3.2 μm, which would be a major hindrance to achieving higher density and higher precision. Also,
For this bird's heak, the completed Tr
However, the accuracy of the design will be extremely poor, and the characteristics of the integrated circuit will also be deteriorated.
一方、ｂｉｒｄ’ｓ ｈｅａｄは１．０／ｊｍの段差が
あるためＡｌ配線時にＡｌの断線、あるいは段着部にお
けるＡｌのエツチング残りによる短絡などが生じ、プロ
セス的に非常に難しく１歩ｖＩＩを悪くする原因となる
。On the other hand, since the bird's head has a step difference of 1.0/jm, disconnection of the Al during Al wiring or short circuit due to residual Al etching at the step part occurs, making the process extremely difficult and making the VII of one step worse. cause
そこで、不発明者らはｂｉｒｃｔ’ｌ ｈｅａｄ 、
ｂｉｒｄ’ｓ ｂｅａｋｆ：なくす方法を提案した。こ
れを第２図に示す。So the non-inventors birct'l head,
bird's beakf: I proposed a method to eliminate it. This is shown in FIG.
１１はたとえばｎ型半導体基板、１２は下地酸化膜、１
３は酸素をｍ過しない窒化ケイ素膜、１４はば化膜でｎ
型半導体基板１１をエツチングして形成した開口部１１
′の側面及び底■に形成されている。１６は１３と同じ
酸素を通過しない窒化ケイ素膜であり、窒化ケイ素膜１
３の端部からｎ型半導体基板を開口した部分の側面にの
み形成さ扛ており、底面には形成さｎていない。この構
造はｎ型半導体基板１１をエツチングする時、第１ステ
ツグとしてケミカルエツチングあるいは等方的なドライ
エツチングによってサイドエツチングをおこしながら開
口し、第２ステツプとして異方性の強いドライエツチン
グによって、マスクパターンに忠実にしかも垂直に所足
重開口した後、酸化膜１４及び窒化ケイ素ｆｉ１５を形
成することにある。版化Ｍ１４はｎ型半導体基板１１を
開口して開口部１１′を形成した後、全面熱ば化するこ
とによって、窒化ケイ素膜１３上には鹸化膜は形成さ扛
ず、ｎ型半導体基板１１を開口した部分にのみ形成する
ことができる。For example, 11 is an n-type semiconductor substrate, 12 is a base oxide film, and 1
3 is a silicon nitride film that does not pass oxygen, and 14 is a nitride film that does not pass oxygen.
Opening 11 formed by etching the semiconductor substrate 11
It is formed on the sides and bottom of . 16 is a silicon nitride film that does not pass oxygen like 13, and silicon nitride film 1
It is formed only on the side surface of the opening of the n-type semiconductor substrate from the end of the substrate 3, and is not formed on the bottom surface. In this structure, when etching the n-type semiconductor substrate 11, the first step is chemical etching or isotropic dry etching to create side etching, and the second step is highly anisotropic dry etching to form a mask pattern. After forming the necessary heavy openings faithfully and vertically, an oxide film 14 and a silicon nitride film 15 are formed. The plate M14 opens the n-type semiconductor substrate 11 to form the opening 11' and then heats the entire surface, so that no saponified film is formed on the silicon nitride film 13 and the n-type semiconductor substrate 11 is heated. can be formed only in the open part.
第２図では熱ば化によってｎ型半導体基板を開口した部
分にのみ鹸化膜１４を形成しているが。In FIG. 2, the saponified film 14 is formed only in the open portion of the n-type semiconductor substrate due to heat evaporation.
ＣＶ Ｄ （Ｃ馳ｍ１ａａｌ Ｖａｐｏｒ Ｄｅｐｏｓ
ｉｔｉｏｎ ）法により、窒化ケイ素膜１３上にも鹸化
膜を形成しても別に構わない。窒化ケイ素膜１６はＣＶ
ＬＩ法により全面形成した後、異方性の強いドライエツ
チングによって、全面エツチングす扛ば、ｎ型半導体基
板を開口した区部部分及び窒化ケイ素僕１３上に形成さ
扛た窒化ケイ素膜１６のみがエツチングさｎ１開口され
た部分の側面に形成さｎた窒化ケイ素−１６のみが自己
整合的に残ることになる。鹸化膜１４は鹸化膜１２と同
Ｌ−ｎ型半導体基板１１に加わる応力を緩和する効果を
待っている。ここで、ｎ型半導体基板１１を開口した部
分の側面にのみ窒化ケイ素膜１５を残す効果は水または
酸素の横方向への供給を防いで、横方向への酸化、すな
わちｂｉ ｒｄ’ｓ ｂｅａｋを発生させないことで
ある。CV D (Cachem1aal Vapor Depos
It is also possible to form a saponified film on the silicon nitride film 13 by the method. The silicon nitride film 16 is CV
After the entire surface is formed by the LI method, if the entire surface is etched by highly anisotropic dry etching, only the silicon nitride film 16 formed on the open section of the n-type semiconductor substrate and the silicon nitride film 13 is removed. Only the silicon nitride 16 formed on the side surface of the etched opening remains in a self-aligned manner. The saponified film 14 is waiting to have the effect of relieving the stress applied to the same Ln type semiconductor substrate 11 as the saponified film 12. Here, the effect of leaving the silicon nitride film 15 only on the side surface of the open portion of the n-type semiconductor substrate 11 is to prevent the supply of water or oxygen in the lateral direction, and to prevent lateral oxidation, that is, bird's beak. This should not be allowed to occur.
水または酸素は開口さｎた部分の底面部にのみ供給され
るので、酸化は縦方向にだけ促進される。Since water or oxygen is supplied only to the bottom of the open section, oxidation is promoted only in the longitudinal direction.
第３図は第２□□□の後、選択酸化した状態である。FIG. 3 shows the selective oxidation state after the second □□□.
１７は選択酸化によって形成された酸化膜であんこの時
、 ｂｉｒｄ’ｓ ｂｅａｋ 、 ｂｉｒｄ’ｓ ｈｅ
ａｄ はほとんど生じないことを我々の実験によって確
認した。17 is an oxide film formed by selective oxidation.
Our experiments confirmed that ad hardly occurs.
しかし、近年においては絶縁分離は素子間分離だけでな
く、１つの素子内の電極間分離にも用いられつつある。However, in recent years, insulation isolation is being used not only for isolation between elements but also for isolation between electrodes within one element.
すなわち、バイポーラトランジスタの場合にはエミッタ
ーコレクタ分離、エミッターベース分離にも絶縁分島が
用いられている。しかし、この電極間分離は素子間分離
と同じ深さだけ行なうと、埋込み部分迄電極間ｆ＋離の
底部が達し、コレクター抵抗が増してしまう。That is, in the case of bipolar transistors, insulating islands are also used for emitter-collector separation and emitter-base separation. However, if this inter-electrode isolation is performed to the same depth as the element-to-element isolation, the bottom of the f+ distance between the electrodes will reach the buried portion, increasing the collector resistance.
不発明は電極間分離酸化族は素子間分離酸化膜よシ浅く
形成出来、しかもバードビークのない分離膜を形成出来
る半導体装置の製造方法を提供せんとするものである。It is an object of the present invention to provide a method for manufacturing a semiconductor device in which an electrode isolation oxide layer can be formed shallower than an element isolation oxide film, and an isolation film without bird's beak can be formed.
すなわち１本発明は電極間分離酸化膜を形成すべき開門
票分を素子間分離酸化膜を形成すべき開口部分より浅く
形成し、この後、電極間分離酸化族を形成すべき開口部
分の底面及び側面、素子間分離酸化膜を形成すべき開口
部分の側面に耐酸化性膜を形成した後、素子間及び電極
間分離酸化膜を形成するものである。That is, one aspect of the present invention is to form the opening portion in which the interelectrode isolation oxide film is to be formed shallower than the opening portion in which the element isolation oxide film is to be formed, and then the bottom surface of the opening portion in which the interelectrode isolation oxide film is to be formed. After forming an oxidation-resistant film on the side surfaces of the opening portion where the element isolation oxide film is to be formed, the element-to-element and inter-electrode isolation oxide films are formed.
以下、不発明に係る構成を図面を用いて説明する。Hereinafter, the configuration according to the invention will be explained using the drawings.
第４図Ａ−Ｆは本発明に係る工程断面図を示す。FIGS. 4A-4F show process cross-sectional views according to the present invention.
同図において、２１はたとえばＰ型半導体基板、２２は
ｎ＋埋込み層、２３はｎｉエピタキシャル層で、１．２
μｍ形成している。２４は下地酸化膜で３００人形成し
てあり、２６はＣＶＤ法によ多形成された１０００人の
窒化ケイ素膜である。２６はフォトリン法によりパター
ニングされたレジスト膜である。In the same figure, 21 is a P-type semiconductor substrate, 22 is an n+ buried layer, 23 is a Ni epitaxial layer, and 1.2
μm is formed. 24 is a 300-layer base oxide film, and 26 is a 1,000-layer silicon nitride film formed by CVD. 26 is a resist film patterned by the photorin method.
このレジスト膜２６をマスクとして窒化ケイ素膜２６を
ドライエツチングし、それから下地醸化＠２４をエツチ
ングして開口＄２７を形成する。Using this resist film 26 as a mask, the silicon nitride film 26 is dry etched, and then the base layer @24 is etched to form an opening $27.
この状態の時、レジスト膜２６は充分残っていもその後
、レジスト膜２６をマスクとしてｎ型エピタキシャル層
２３を０．３μｍドライエ、チングする。In this state, even if a sufficient amount of the resist film 26 remains, the n-type epitaxial layer 23 is then etched by dry etching to a thickness of 0.3 μm using the resist film 26 as a mask.
この部分はエミッター、コレクター分離領域となる部分
である。This part becomes the emitter and collector separation area.
その後、レジスト＆２８を付着させ、７オトリン法によ
りパターニングする。そして、ト１ライエツチング法で
エピタキシャル層２３をエツチングして開口部２９を形
成する。この深さは０．７６μｍである。（第４図Ｂ）
その後、レジスト膜２８を除去し、熱酸化により酸化膜
３０をＳＯＯ人形底形成。この酸化膜３０はｎ撤エピタ
キシャル６２３を開口した部分にのみ形成され、窒化ケ
イ素＠２６上には形成されていない。しかし、この酸化
膜形成方法はＣＶＤ法により全面に形成しても別に構わ
ない。その後、全面に窒化ケイ素膜３１を１０００人形
成する。（第４図Ｃ）
次に異方性の強いドライエ、チング反応スバ。Thereafter, a resist &28 is applied and patterned using the 7-otrine method. Then, the epitaxial layer 23 is etched using a tri-etching method to form an opening 29. This depth is 0.76 μm. (FIG. 4B) After that, the resist film 28 is removed and an oxide film 30 is formed on the bottom of the SOO doll by thermal oxidation. This oxide film 30 is formed only on the opening of the n-evacuation epitaxial layer 623, and is not formed on the silicon nitride @26. However, this oxide film formation method may be performed by CVD method to form the entire surface. Thereafter, 1000 silicon nitride films 31 are formed over the entire surface. (Figure 4C) Next is the dryer and ching reaction suba, which has strong anisotropy.
タエッチングあるいはイオンエツチングによって、全面
エツチングする。このエツチングの時、異方性が強いた
め縦方向にはエツチングされるが、ｍ方間にはエツチン
グされないため、開口した部分の側面に形成された窒化
膜３２のみが自己整合的に残ることになる。（第４図Ｄ
）
その後、全面酸化をすると露出したエピタキシャル層２
３に形成された開口部３３．３４の深さが異なるため、
開口部３４の深さに合わせて酸化すると、開口ｆｌｓ３
３では酸化膜の盛り上がりが大きくなシすぎることとな
る。これを防ぐために、１００〜３００人程度ノ憔＜薄
イ５ｉ５Ｎ４膜３６を開口部３３の底面につける。（第
４図Ｅ）この形成方法として、たとえば開口ｆｆＢ５３
のみを開口したホトレジストをつけ、その上に全面にプ
ラズマ５ｉｓＮ４膜を付着させ、その後り７トオフする
ことによっても得られる。又、全面にｂｉｓＮ４１薄く
付着させ、その後通常のホ） ＩＪン技術を使って、開
口部３３以外の部分の５ｉ５Ｎ４をエッチオフしても得
られるが、いずれの方法を用いても良い。The entire surface is etched by etching or ion etching. During this etching, due to the strong anisotropy, it is etched in the vertical direction, but it is not etched in the m direction, so only the nitride film 32 formed on the side surfaces of the opening remains in a self-aligned manner. Become. (Figure 4D
) Then, when the entire surface is oxidized, the exposed epitaxial layer 2
Since the depths of the openings 33 and 34 formed in 3 are different,
When oxidized according to the depth of the opening 34, the opening fls3
3, the swell of the oxide film becomes too large. To prevent this, a thin 5i5N4 film 36 of about 100 to 300 layers is applied to the bottom of the opening 33. (FIG. 4E) As this forming method, for example, the opening ffB53
It can also be obtained by applying a photoresist with openings only, depositing a plasma 5isN4 film on the entire surface, and then removing the rest. Alternatively, it can be obtained by depositing a thin layer of bisN41 on the entire surface and then etching off the 5i5N4 in the area other than the opening 33 using a conventional IJ technique, but any method may be used.
その後、選択傷化することによって酸化膜３６゜３７を
１．６μｍ形成する。この酸化は高王販化を用いれば１
ｏｏＯ℃、６，６￥ｉの条件で約９０分と短い時間でば
化ができ、ｎ＋埋込み層２２の持ち上がりも少なく、耐
圧を高くすることができる。このような方法によ扛ば、
ｂｉｒｄ’ｓ ｂｅａｋはほとんどな（、ｂｉｒｄ’
ｓ ｈｅａｄは全く生じておらず、しかも電極間分離酸
化膜３７は浅く形成さ扛ている。ここで、酸化膜３７は
浅く形成されているのでコレクタ抵抗が増大することは
ない。この状態で分離は完成している。（第４肉Ｆ）
第４図Ｇは分離が終わった後、バイポーラトランジスタ
を形成した状態を示している。３７はペースとコレクタ
を分離している取化膜、３８は活性ペース層を形成して
いるＰ−領域、３９はｐｏｌｙＳｔ、 ４０ｉｔ、エ
ミ、りとペース・コンタクトを分離している酸化膜、４
１はｎ領域で、４２はエミッタ、４２はコレクタ・コン
タクトを形成している。４３はｐ＋９５４域で不活性ペ
ース層の抵抗を下げているとともにペース・コンタクト
も形成している。４４はＡｌ配線である。また、４６は
フィールド酸化膜である。Thereafter, an oxide film 36° 37 with a thickness of 1.6 μm is formed by selective scratching. This oxidation can be reduced to 1 by using Kohanka.
Under the conditions of 00° C. and 6.6 yen i, the curing can be carried out in a short time of about 90 minutes, the lifting of the n+ buried layer 22 is small, and the withstand voltage can be increased. If you use this method,
Almost no bird's beak (, bird'
No shead is formed at all, and the interelectrode isolation oxide film 37 is formed shallowly. Here, since the oxide film 37 is formed shallowly, the collector resistance does not increase. In this state, separation is complete. (Fourth material F) FIG. 4 G shows a bipolar transistor formed after separation. 37 is an absorption film separating the paste and collector, 38 is a P- region forming an active paste layer, 39 is polySt, 40it is an oxide film separating the emitter and the paste contact, 4
1 is an n region, 42 is an emitter, and 42 is a collector contact. 43 lowers the resistance of the inactive paste layer in the p+954 region and also forms a paste contact. 44 is an Al wiring. Further, 46 is a field oxide film.
以上述べてきたように、本発明は電極間分離酸化膜を素
子間分離酸化膜より浅く形成出来るので、ｙすえばコレ
クタ抵抗が増大するといった問題がな−−い。しかも、
電極開存び素子間分離酸化膜を形成すべき開口部側面に
窒化ケイ素膜を安定に残すことによって選択酸化時に生
じるｂｉｒｄ’ｓ ｂｅａｋを極力減少させ、ｂｉｒｄ
’ｓ ｈｅａｄは全く生じないという効果を持つている
。ｂｉｒｄ’ｓ ｂｅａｋを最大限防いでいることによ
り、トランジスタの活性領域のつぶれは非常に少なくな
り、高密度化、高精度化に寄与している。ｂｉｒｄ’ｓ
ｈｅａｄは全く生じないため。As described above, in the present invention, since the interelectrode isolation oxide film can be formed shallower than the element isolation oxide film, there is no problem of increased collector resistance. Moreover,
By stably leaving a silicon nitride film on the side surface of the opening where the electrode opening and the element isolation oxide film are to be formed, the bird's peak that occurs during selective oxidation is reduced as much as possible, and the bird's
's head has the effect of not occurring at all. By preventing bird's beak to the maximum extent possible, collapse of the active region of the transistor is extremely reduced, contributing to higher density and higher precision. bird's
Because head is not generated at all.
シリコン基板表面は平担で、ＡＩ配線時における段差部
での断線あるいはエッチ残りによる短絡もおこらず、プ
ロセスが安定しているため歩留の向上につながっている
。また、シリコン基板を開口した部分の側面に窒化ケイ
素膜を残すことは、選択酸化時にシリコン基板に加わる
応力を緩和する効果をも有し、従来に比べて結晶欠陥が
非常に少ないという利点があり、トランジスタの歩留向
上にも大いに役立っている。The silicon substrate surface is flat, and there are no disconnections at stepped portions or short circuits due to etch residue during AI wiring, and the process is stable, leading to improved yields. Additionally, leaving a silicon nitride film on the side surface of the opening in the silicon substrate has the effect of alleviating the stress applied to the silicon substrate during selective oxidation, and has the advantage of significantly fewer crystal defects than conventional methods. This has also greatly helped improve the yield of transistors.
以上のように不発明は高密度化、高精度化２歩留向上を
翻った半導体装置の製造方法に大きく寄゛、ＭＬ、また
１猶的にも非常に価値の高いものである。As described above, the invention greatly depends on the manufacturing method of semiconductor devices that has increased density, precision, and yield improvement, and is extremely valuable in terms of ML and also in terms of production.
第１図ａ、ｂは従来の絶縁分離方法による工程図、第２
図は先に提案した半導体基板の構造断面図、第３図は先
に提案した絶縁分離の要部断面図。
第４図Ａ−Ｇは本発明の一実施例にかかる半導体装置の
要部製造工程図である。
３０・・・・・・酸化・膜％ ３２・・・・・・シリコ
ン基板を開口した部分の側面にのみ残っている窒化ケイ
素膜、３６ 、３７・・・・・・撰択酸化により形成さ
れた分離酸化膜、３３．３４・・・・・・エツチングに
よる開口部。
代理人の氏名 弁理士 中 尾 敏 男 ほか１多筒
１ 図
＊２ 醐
！Ｉ！３ＦＲFigures 1a and b are process diagrams for the conventional insulation isolation method;
The figure is a cross-sectional view of the structure of the semiconductor substrate proposed earlier, and FIG. 3 is a cross-sectional view of the main part of the insulation isolation proposed earlier. FIGS. 4A to 4G are process diagrams for manufacturing essential parts of a semiconductor device according to an embodiment of the present invention. 30...Oxidation/film% 32...Silicon nitride film remaining only on the side surface of the open portion of the silicon substrate, 36, 37...... Formed by selective oxidation Isolation oxide film, 33.34...Opening by etching. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure *2 Go! I! 3FR
Claims (2)
形成する工程と、前記第２及び第１の絶縁膜を開口して
開口部を形成する工程と、前記開口部下の前記半導体基
板を深さを変えて開口する工程と、少なくとも前記半導
体基板を開口した領域に第３の絶縁膜を形成する工程と
、前記第１．第２の絶縁膜の開口部及び前記半導体基板
を開口した領域の側面部にのみ第４の絶縁膜を形成する
工程と、前記半導体基板のうち浅い開口した領域の底面
に第６の絶縁膜を残す工程と、前記第２．第４の絶縁ｌ
ＩＱをマスクに前記半導体基板を酸化する工程とを備え
たことを特徴とする半導体装置の製造方法。(1) A step of forming a first insulating film and a second insulating film on a semiconductor substrate, a step of opening the second and first insulating films to form an opening, and a step of forming an opening under the opening. forming an opening in the semiconductor substrate at different depths; forming a third insulating film at least in the region of the opening in the semiconductor substrate; forming a fourth insulating film only on the opening of the second insulating film and the side surface of the region of the semiconductor substrate where the opening is made; and forming a sixth insulating film on the bottom surface of the shallowly opened region of the semiconductor substrate. the second step; Fourth insulation l
A method for manufacturing a semiconductor device, comprising the step of oxidizing the semiconductor substrate using IQ as a mask.
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(2) Second. 4th. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the sixth insulating film is a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2624382A JPS58142540A (en) | 1982-02-19 | 1982-02-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2624382A JPS58142540A (en) | 1982-02-19 | 1982-02-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58142540A true JPS58142540A (en) | 1983-08-24 |
Family
ID=12187852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2624382A Pending JPS58142540A (en) | 1982-02-19 | 1982-02-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58142540A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432984A (en) * | 1977-08-19 | 1979-03-10 | Hitachi Ltd | Integrated circuit device |
| JPS56142667A (en) * | 1980-03-13 | 1981-11-07 | Ibm | Semiconductor device |
-
1982
- 1982-02-19 JP JP2624382A patent/JPS58142540A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432984A (en) * | 1977-08-19 | 1979-03-10 | Hitachi Ltd | Integrated circuit device |
| JPS56142667A (en) * | 1980-03-13 | 1981-11-07 | Ibm | Semiconductor device |
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