JPS5814095B2 - Waveform shaping circuit - Google Patents
Waveform shaping circuitInfo
- Publication number
- JPS5814095B2 JPS5814095B2 JP53001364A JP136478A JPS5814095B2 JP S5814095 B2 JPS5814095 B2 JP S5814095B2 JP 53001364 A JP53001364 A JP 53001364A JP 136478 A JP136478 A JP 136478A JP S5814095 B2 JPS5814095 B2 JP S5814095B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- input signal
- waveform
- voltage dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
この発明は例えば継電器に与える入力信号波形をパルス
状にして供給するための波形整形回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping circuit for supplying, for example, an input signal waveform to a relay in the form of a pulse.
従来の波形整形回路は固定の基準電圧を持つ比較器に波
形整形する信号を比較入力として印加し入力信号が基準
電圧レベル以上あわか否かで、比較器の出力が2値状態
を変えるものであった。Conventional waveform shaping circuits apply a waveform shaping signal as a comparison input to a comparator with a fixed reference voltage, and the output of the comparator changes its binary state depending on whether or not the input signal exceeds the reference voltage level. there were.
このため、入力信号の電圧変化が広範囲になる場合、比
較器の基準電圧は常時ノイズレベルを捕えない程度に充
分低くする必要があった。For this reason, when the input signal voltage changes over a wide range, the reference voltage of the comparator needs to be sufficiently low so as not to capture the noise level at all times.
従って、入力信号レベルが高い場合にも比較基準の低い
レベルと比較することになり、入力信号に含まれる歪、
ノイズ等のため、出力位相や信号幅が所期のものと異な
る等の弊害が生じていた。Therefore, even if the input signal level is high, it will be compared with the low level of the comparison standard, and the distortion contained in the input signal will be
Due to noise and the like, problems such as the output phase and signal width being different from the expected ones have occurred.
この発明は上記に鑑みてなされ、入力信号レベルに応じ
て基準電圧を自動的に変化させて、入力信号の変動範囲
が大きい場合にもノイズや歪等を確実に除去することが
できる波形整形回路を提供することを目的とする。This invention has been made in view of the above, and is a waveform shaping circuit that can automatically change the reference voltage according to the input signal level and reliably remove noise, distortion, etc. even when the fluctuation range of the input signal is large. The purpose is to provide
以下図面を参照してこの発明の一実施例を説明する。An embodiment of the present invention will be described below with reference to the drawings.
第1図において、1は入力信号が供給される入力端子で
、この入力端子1は第1分圧回路2を介して零電位部に
接続される。In FIG. 1, reference numeral 1 denotes an input terminal to which an input signal is supplied, and this input terminal 1 is connected to a zero potential section via a first voltage dividing circuit 2.
第1分圧回路2は抵抗2a,2bからなり、両抵抗2a
,2bの中点2cは演算増幅器3の非反転入力端に接続
される。The first voltage dividing circuit 2 consists of resistors 2a and 2b, both resistors 2a and 2b.
, 2b is connected to the non-inverting input terminal of the operational amplifier 3.
演算増幅器3の出力端は図示極性のダイオード4を介し
て第2分圧回路5に接続される。The output terminal of the operational amplifier 3 is connected to a second voltage dividing circuit 5 via a diode 4 having the polarity shown.
第2分圧回路5は抵抗5a,sbからなり、両抵抗5a
,5bの中点5cに前記ダイオード4が接続されるとと
もに演算増幅器3の反転入力端が接続される。The second voltage dividing circuit 5 consists of resistors 5a and sb, both resistors 5a
, 5b is connected to the diode 4 and to the inverting input terminal of the operational amplifier 3.
抵抗5a,5bの一端は正の基準電圧源(Vref)に
接続され、他端は零電位部に接続される。One ends of the resistors 5a and 5b are connected to a positive reference voltage source (Vref), and the other ends are connected to a zero potential section.
6はピークホールド回路を形成するコンデンサで、この
コンデンサ6の一端は前記中点5cに接続され、他端は
零電位部に接続される。A capacitor 6 forms a peak hold circuit, one end of which is connected to the midpoint 5c, and the other end connected to the zero potential section.
Tは比較器回路で、この比較器回路7の反転入力端は前
記中点5cに接続され、非反転入力端は入力端子1に接
続される。T is a comparator circuit, and the inverting input terminal of this comparator circuit 7 is connected to the midpoint 5c, and the non-inverting input terminal is connected to the input terminal 1.
比較器回路7の出力端は出力端子8に接続される。The output terminal of comparator circuit 7 is connected to output terminal 8 .
次に上記実施例の作用を第2図a〜cを用いて述べる。Next, the operation of the above embodiment will be described using FIGS. 2a to 2c.
定し、また、入力が零の時の第2分圧回路5の分圧値を
V1ど設定すると、v1はVref−R4/Ra+R4
となる。If the voltage division value of the second voltage division circuit 5 when the input is zero is set to V1, then v1 becomes Vref-R4/Ra+R4.
becomes.
但し、R1,R2は抵抗2a,2b,R3rR4は抵抗
5a,5bである。However, R1 and R2 are resistors 2a and 2b, and R3rR4 are resistors 5a and 5b.
上記のような条件のとき入力端子1に入力信号MINが
到来する。An input signal MIN arrives at the input terminal 1 under the above conditions.
この入力信号vINが■1×点5cの電圧v2は第2図
aに示すV1レベルなる,越える正電圧になると、前記
電圧v2のレベルが上昇する。When this input signal vIN becomes a positive voltage that exceeds the voltage v2 at point 5c (1×1), which is the V1 level shown in FIG. 2a, the level of the voltage v2 rises.
このレベル上昇値はピークホールド回路を形成するコン
デンサ6のため、入力信号VINこの電圧はコンデンサ
6に充電される。Since this level rising value is applied to the capacitor 6 forming a peak hold circuit, the capacitor 6 is charged with this voltage of the input signal VIN.
その後、入力信号VINが小さくなっても、前記電圧v
2のレベルはコンデンサ6の容量と抵抗5a,sbの抵
抗値との時定数で決定される時間で徐々に放電して降下
する。After that, even if the input signal VIN becomes small, the voltage v
The level of 2 is gradually discharged and lowered in a time determined by the time constant of the capacitance of the capacitor 6 and the resistance values of the resistors 5a and sb.
この電圧■2のレベルを基準電圧として入力信号VIN
と比較回路7で比較すると、出力端子8には第2図bに
示すような整形波形が得られる。The input signal VIN is set using the level of this voltage ■2 as a reference voltage.
When compared by the comparator circuit 7, a shaped waveform as shown in FIG. 2b is obtained at the output terminal 8.
このような整形波形は基準電圧v2が入力信号VINに
より変動させたことにより得られるが、この基準電圧を
従来のように固定基準電圧とすると第2図Cに示すよう
な入力信号VINの歪やノイズ等が整形されて図のよう
なパルスP1〜P3が生じてしまう。Such a shaped waveform is obtained by varying the reference voltage v2 with the input signal VIN, but if this reference voltage is fixed as in the past, the input signal VIN will be distorted as shown in Figure 2C. Noise etc. are shaped and pulses P1 to P3 as shown in the figure are generated.
第3図はこの発明の他の実施例を示すもので、第1図と
同一部分は同一符号を付して説明を省略する。FIG. 3 shows another embodiment of the present invention, in which the same parts as in FIG. 1 are given the same reference numerals and their explanation will be omitted.
第3図において、前記実施例の第1分圧回路に代えて、
入力端子1と演算増幅器3のプラス入力端との間にロー
パスフィルタ回路9を介装したものである。In FIG. 3, instead of the first voltage dividing circuit of the above embodiment,
A low-pass filter circuit 9 is interposed between the input terminal 1 and the positive input terminal of the operational amplifier 3.
このローパスフィルタ回路9は入力信号の高周波成分を
除去するのが目的であるから、しゃ断周波数は広範囲に
設定できるが、この実施例では入力信号の基本周波数程
度に設定した,次に上記実施例の作用を述べる。Since the purpose of this low-pass filter circuit 9 is to remove high frequency components of the input signal, the cutoff frequency can be set over a wide range, but in this embodiment, it is set to about the fundamental frequency of the input signal. Describe the effect.
入力信号VINが第4図aに示すような波形であるとす
ると、ローパスフィルタ回路9の出力は第4図aに示す
ように入力信号VINより振幅が小さくかつ位相が遅れ
た電圧波形■3となる。Assuming that the input signal VIN has a waveform as shown in FIG. 4a, the output of the low-pass filter circuit 9 is a voltage waveform 3 whose amplitude is smaller and the phase is delayed than that of the input signal VIN, as shown in FIG. 4a. Become.
但し、中点5cの電圧をv5、入力が0の時のバスフィ
ルタ回路9の出力の正電圧の最大値がv1より小さい場
合には第4図aに示すようv5=v1となる。However, if the voltage at the midpoint 5c is v5 and the maximum value of the positive voltage output from the bus filter circuit 9 when the input is 0 is smaller than v1, then v5=v1 as shown in FIG. 4a.
これはダイオード4の影響である。前記分圧値v1は入
力信号VINが予想される最小の場合でも比較器回路7
により整形可能に設定される。This is the effect of diode 4. The voltage division value v1 is determined by the comparator circuit 7 even when the input signal VIN is at the expected minimum.
It is set to be formattable by .
前記ローパスフィルタ9の出力の正電圧の最大値が分圧
値v1を越える場合はダイオード4、コンデンサ6のた
め、第4図aに示す電圧波形v3の正電圧のピークレベ
ルに一致する電圧にコンデンサ6は充電される。If the maximum value of the positive voltage output from the low-pass filter 9 exceeds the voltage division value v1, the diode 4 and capacitor 6 cause the capacitor to rise to a voltage that matches the peak level of the positive voltage of the voltage waveform v3 shown in FIG. 4a. 6 is charged.
その後、コンデンサ6の充電々圧は抵抗5a,sbおよ
びコンデンサ6の時定数で決まる時間で徐々に放電され
、第4図aに示す電圧波形v5のようになる。Thereafter, the charging voltage of the capacitor 6 is gradually discharged at a time determined by the resistors 5a, sb and the time constant of the capacitor 6, and the voltage waveform becomes like the voltage waveform v5 shown in FIG. 4a.
この電圧波形v5が比較基準電圧となって比較器回路7
で入力信号vINは比較整形されて第4図bのような波
形となる。This voltage waveform v5 becomes the comparison reference voltage and the comparator circuit 7
The input signal vIN is compared and shaped to have a waveform as shown in FIG. 4b.
なお、第4図Cは従来の固牢基準電圧を用いて入力信号
VINを波形整形したときのもので、この場合は前記実
施例と同様に歪やノイズ等まで整形されてしまうこさを
示す。Incidentally, FIG. 4C shows the waveform of the input signal VIN when the conventional fixed reference voltage is used to shape the waveform. In this case, it is shown that distortion, noise, etc. are also shaped as in the previous embodiment.
また、前記両実施例においては入力信号の正電圧部分を
整形する場合について述べて来たが、負電圧部分を整形
する場合についても基準電圧源(Vref)を負電圧と
し、ダイオード4の極性を逆極性にすれば同様の効果が
得られる。Furthermore, in both of the above embodiments, the case where the positive voltage part of the input signal is shaped has been described, but when shaping the negative voltage part, the reference voltage source (Vref) is set to a negative voltage, and the polarity of the diode 4 is changed. A similar effect can be obtained by using reverse polarity.
以上述べたようにこの発明によれば、基準電圧源の分圧
値より大きい入力信号のみを抽出し、その抽出々力のピ
ーク値を保持するピークホールド回路を設け、このピー
クホールド値と入力信号とを比較するようにしたので、
入力信号が広範囲に渡って変化する場合にも、比較基準
レベルを常に最適な値に制御できるため、入力信号に含
まれるノイズや歪等を整形することなく、所望の整形波
形が得られる事になり回路の制御の信頼性が高い利点が
ある。As described above, according to the present invention, a peak hold circuit is provided which extracts only the input signal larger than the divided voltage value of the reference voltage source and holds the peak value of the extracted power, and the peak hold value and the input signal are I tried to compare it with
Even when the input signal changes over a wide range, the comparison reference level can always be controlled to the optimal value, so the desired shaped waveform can be obtained without having to shape the noise or distortion contained in the input signal. This has the advantage of high reliability of circuit control.
第1図はこの発明の一実施例を示す回路図、第2図a”
cは第1図の作用を述べるための波形図、第3図はこの
発明の他の実施例を示す回路図、第4図a”cは第3図
の作用を述べるための波形図である。
1……入力端子、2……第1分圧回路、3……演算増幅
器、4……ダイオード、5……第2分圧回路、6……コ
ンデンサ、7……比較器回路、8……出力端子、9……
ローパスフィルタ回路。Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 a''
FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 a"c is a waveform diagram explaining the action of FIG. 3. 1... Input terminal, 2... First voltage divider circuit, 3... Operational amplifier, 4... Diode, 5... Second voltage divider circuit, 6... Capacitor, 7... Comparator circuit, 8... ...Output terminal, 9...
Low pass filter circuit.
Claims (1)
圧する第2分圧回路と、前記第1分圧回路の分圧点は一
方の入力端に、他方の反転入力端には前記第2分圧回路
の分圧点が接続され、かつ出力端はダイオードを介して
第2分圧回路の分圧点に接続され、前記第2分圧回路の
分圧値より大きい入力信号のみのときだけ出力する演算
増幅器と前記第2分圧回路の分圧点に接続され、その分
圧点の出力のピーク値を保持するピークホールド回路と
、このピークホールド回路の保持電圧と入力信号とを比
較し、出力に整形出力を送出する比較回路とを備えたこ
とを特徴とする波形整形回路。1 A first voltage divider circuit that divides the human power signal, a second voltage divider circuit that divides the reference voltage, and the voltage division point of the first voltage divider circuit is connected to one input terminal, and the other inverting input terminal is connected to the voltage divider circuit that divides the reference voltage. The voltage dividing point of the second voltage dividing circuit is connected, and the output terminal is connected to the voltage dividing point of the second voltage dividing circuit via a diode, and only input signals larger than the voltage dividing value of the second voltage dividing circuit are connected. an operational amplifier that outputs only when 1. A waveform shaping circuit comprising: a comparison circuit that performs comparison and sends a shaped output as an output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53001364A JPS5814095B2 (en) | 1978-01-10 | 1978-01-10 | Waveform shaping circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53001364A JPS5814095B2 (en) | 1978-01-10 | 1978-01-10 | Waveform shaping circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5494263A JPS5494263A (en) | 1979-07-25 |
JPS5814095B2 true JPS5814095B2 (en) | 1983-03-17 |
Family
ID=11499434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53001364A Expired JPS5814095B2 (en) | 1978-01-10 | 1978-01-10 | Waveform shaping circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5814095B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63187859U (en) * | 1987-05-27 | 1988-12-01 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57185708A (en) * | 1981-05-11 | 1982-11-16 | Hitachi Ltd | Amplifying circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB997949A (en) * | 1961-07-14 | 1965-07-14 | Rank Bush Murphy Ltd | Improved signal limiting circuit arrangement |
-
1978
- 1978-01-10 JP JP53001364A patent/JPS5814095B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB997949A (en) * | 1961-07-14 | 1965-07-14 | Rank Bush Murphy Ltd | Improved signal limiting circuit arrangement |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63187859U (en) * | 1987-05-27 | 1988-12-01 |
Also Published As
Publication number | Publication date |
---|---|
JPS5494263A (en) | 1979-07-25 |
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