JPH0728736Y2 - Voltage-frequency conversion circuit - Google Patents
Voltage-frequency conversion circuitInfo
- Publication number
- JPH0728736Y2 JPH0728736Y2 JP14119488U JP14119488U JPH0728736Y2 JP H0728736 Y2 JPH0728736 Y2 JP H0728736Y2 JP 14119488 U JP14119488 U JP 14119488U JP 14119488 U JP14119488 U JP 14119488U JP H0728736 Y2 JPH0728736 Y2 JP H0728736Y2
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- operational amplifier
- voltage
- capacitor
- resistor
- output
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Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、電圧制御により周波数発振を行なう電圧−周
波数変換回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a voltage-frequency conversion circuit that oscillates frequency by voltage control.
従来において、電圧−周波数変換回路（以下Ｖ−Ｆ変換
回路と称す）としては、第３図に示す回路が提案されて
いる。図において、Ａは積分回路であって、１は演算増
幅器、C1は積分用コンデンサで、一端は演算増幅器１の
反転入力端子に、他端は出力端子に接続される。R1は入
力電圧VINより電流を供給する充電用抵抗にして、演算
増幅器１の反転入力端子に接続される。Conventionally, a circuit shown in FIG. 3 has been proposed as a voltage-frequency conversion circuit (hereinafter referred to as a VF conversion circuit). In the figure, A is an integrating circuit, 1 is an operational amplifier, C 1 is an integrating capacitor, one end of which is connected to the inverting input terminal of the operational amplifier 1 and the other end of which is connected to the output terminal. R 1 is a charging resistor that supplies a current from the input voltage V IN , and is connected to the inverting input terminal of the operational amplifier 1.
R2はコンデンサC1に蓄積された電荷の放電用抵抗で、一
端は演算増幅器１の反転入力端子に、他端は後述するト
ランジスタ３のコレクタに接続される。R3及びR4は直列
に接続され、入力電圧VINを分圧することにより基準電
圧R4／（R3＋R4）を演算増幅器１の非反転入力端子に供
給する抵抗である。R 2 is a resistor for discharging the electric charge accumulated in the capacitor C 1 , one end of which is connected to the inverting input terminal of the operational amplifier 1 and the other end of which is connected to the collector of the transistor 3 described later. R 3 and R 4 are resistors that are connected in series and supply the reference voltage R 4 / (R 3 + R 4 ) to the non-inverting input terminal of the operational amplifier 1 by dividing the input voltage V IN .
Ｂはコンパレータであって、２は演算増幅器、R5は演算
増幅器１の出力を演算増幅器２の反転入力端子に供給す
る抵抗、R7及びR8は演算増幅器２の非反転入力端子に比
較電位を与える抵抗、R6は演算増幅器２の出力端子より
非反転入力端子に接続され、ヒステリシスを与える抵抗
である。B is a comparator, 2 is an operational amplifier, R 5 is a resistor for supplying the output of the operational amplifier 1 to the inverting input terminal of the operational amplifier 2, and R 7 and R 8 are comparison potentials at the non-inverting input terminal of the operational amplifier 2. , R 6 is a resistor that is connected from the output terminal of the operational amplifier 2 to the non-inverting input terminal to give a hysteresis.
Ｃは放電回路であって、３は放電用トランジスタ、R9は
演算増幅器２の出力をトランジスタ３のベースに供給す
る抵抗である。C is a discharging circuit, 3 is a discharging transistor, and R 9 is a resistor for supplying the output of the operational amplifier 2 to the base of the transistor 3.
而して、前記した構成においてその動作を第４図を用い
説明するに、入力電圧VINが印加されると、演算増幅器
１の反転入力端子電圧（以下V1 -と称す）は非反転入力
端子電圧（以下V1 +と称す）より低いレベルであるた
め、演算増幅器１の出力電圧（以下V0と称す）はHiレベ
ルとなり、演算増幅器２の出力電圧（以下VOUTと称す）
はLowレベルとなる。このため、放電用トランジスタ３
はOFFの状態を維持する。Thus, in order to explain the operation in the above-mentioned configuration with reference to FIG. 4, when the input voltage V IN is applied, the inverting input terminal voltage (hereinafter referred to as V 1 − ) of the operational amplifier 1 is a non-inverting input. Since the level is lower than the terminal voltage (hereinafter referred to as V 1 + ), the output voltage of the operational amplifier 1 (hereinafter referred to as V 0 ) becomes Hi level, and the output voltage of the operational amplifier 2 (hereinafter referred to as V OUT )
Becomes Low level. Therefore, the discharging transistor 3
Keeps OFF.
更に、コンデンサC1に電荷が蓄積され、演算増幅器１の
（V1 -）が（V1 +）のレベルを超えると演算増幅器１の出
力電圧V0はLowレベルに変化し、演算増幅器２の反転入
力端子電圧が非反転入力端子電圧より低いレベルとなる
ため演算増幅器２の出力電圧VOUTはHiレベルとなる。こ
のため、放電用トランジスタ３がON状態となり、抵抗R2
を通してコンデンサC1に蓄積された電荷を放電し始め
る。この放電により、演算増幅器１の（V1 -）が（V1 +）
より低いレベルになると、再び演算増幅器１の出力電圧
V0はHiレベルとなり、演算増幅器２の出力電圧VOUTがLo
wレベルとなり、トランジスタ３がOFFとなって再びコン
デンサC1は充電を始める。Furthermore, when electric charge is accumulated in the capacitor C 1 and (V 1 − ) of the operational amplifier 1 exceeds the level of (V 1 + ), the output voltage V 0 of the operational amplifier 1 changes to the Low level, and Since the inverting input terminal voltage becomes a level lower than the non-inverting input terminal voltage, the output voltage V OUT of the operational amplifier 2 becomes Hi level. Therefore, the discharging transistor 3 is turned on and the resistor R 2
Starts to discharge the electric charge accumulated in the capacitor C 1 through. This discharge of the operational amplifier 1 (V 1 -) is (V 1 +)
At a lower level, the output voltage of the operational amplifier 1 is again
V 0 becomes Hi level, and the output voltage V OUT of the operational amplifier 2 becomes Lo
At w level, transistor 3 turns off and capacitor C 1 starts charging again.
一般に、この種のＶ−Ｆ変換回路において、充電時間を
t1、放電時間をt2、充電電流をIc、放電電流をId，ヒス
テリシス幅をVTHとすると、次の式が成り立つ。Generally, in this type of VF conversion circuit, the charging time is
Let t 1 , discharge time be t 2 , charge current be I c , discharge current be I d , and hysteresis width be V TH .
t1＝C1・VTH／Ic t2＝C1・VTH／Id ここに、Ic＝VIN／（2R1） Id＝（VIN/2） ×（1/R2−1/R1） VTH＝〔R7R8／（R7R8＋R6）〕 ×（VOH−VOL） 但し、R3＝R4，R1＞R2 VOH及びVOLは演算増幅器２の出力がHiのときとLowのと
きの飽和出力電圧であり、VOH及びVOLと抵抗R6の大きさ
によって演算増幅器２の非反転入力端子の電位が変化
し、この電位の差をVthとしており、このVthは、詳細な
計算式を省略しているが上式のようになる。t 1 = C 1 · V TH / I c t 2 = C 1 · V TH / I d where I c = V IN / (2R 1 ) I d = (V IN / 2) × (1 / R 2 −1 / R 1 ) V TH = [R 7 R 8 / (R 7 R 8 + R 6 )] × (V OH −V OL ) where R 3 = R 4 , R 1 > R 2 V OH and V OL Is the saturated output voltage when the output of the operational amplifier 2 is Hi and Low, and the potential of the non-inverting input terminal of the operational amplifier 2 changes depending on the sizes of V OH and V OL and the resistance R 6 , and this potential the difference of which the V th, the V th does not have the detailed formula is as above equation.
コンパレータＢの出力が放電回路Ｃを通じて積分回路Ａ
の積分用コンデンサC1の放電を制御しているので、積分
回路Ａの出力はVthの電位差で充放電を繰り返し、ヒス
テリシス幅Vthは積分回路Ａの充放電振幅を規定するも
のである。The output of the comparator B passes through the discharge circuit C and the integration circuit A
Since the control of the discharge of the integrating capacitor C 1, the output of the integrating circuit A repeatedly charged and discharged at a potential difference of V th, the hysteresis width V th is to define the charge and discharge amplitude of the integrating circuit A.
また、発振周波数ｆは次式で与えられる。The oscillation frequency f is given by the following equation.
ｆ＝1/（t1＋t2） 〔考案が解決しようとする課題〕 ところで、前記したＶ−Ｆ変換回路にあっては、一般的
にはコンデンサC1が小さく、発振周波数も高いため、コ
ンデンサC1における充放電時間は余り問題とならない
が、発振周波数を低く設定した場合にはコンデンサC1の
値が比較的大きな値となり、このため入力電圧VINのレ
ベル変化（例えば減少方向）の割合が放電時間t2に比べ
て速く、大きい場合には、積分回路Ａの基準電圧V1 +は
入力電圧VINに追従するが、（V1 -）は変化前の高いレベ
ルの入力電圧VINにより蓄積されたコンデンサC1の電荷
の放電のため、変化後低い入力電圧VINによる（V1 -）に
達する時間が長くなり、追従性が悪くなる。f = 1 / (t 1 + t 2 ) [Problems to be solved by the invention] By the way, in the VF conversion circuit described above, the capacitor C 1 is generally small and the oscillation frequency is high. The charging / discharging time at C 1 does not matter so much, but when the oscillation frequency is set low, the value of the capacitor C 1 becomes a relatively large value, and therefore the level change (for example, decreasing direction) of the input voltage V IN There faster than the discharging time t 2, is greater, although the reference voltage V 1 + the integration circuit a to follow the input voltage V iN, (V 1 -) input voltage V iN of high level before the change for discharge of the accumulated in the capacitor C 1 charges by, according to the following low input voltage V iN changes (V 1 -) time increases to reach, trackability becomes worse.
第４図に入力電圧VINの電圧波形（ａ）に対する出力電
圧VOUTの電圧波形（ｂ）を示す。この出力波形（ｂ）の
t0の部分が入力電圧VINの急激な変化に追従できないこ
とを示している。この現象は入力電圧VINが増加方向へ
急激に変化する場合でも同様である。以上の如く、従来
のＶ−Ｆ変換回路においては、急激な入力電圧の変化に
対してはＶ−Ｆ変換機能が充分に働かないという問題点
があった。FIG. 4 shows the voltage waveform (b) of the output voltage V OUT with respect to the voltage waveform (a) of the input voltage V IN . This output waveform (b)
It shows that the part of t 0 cannot follow the rapid change of the input voltage V IN . This phenomenon is the same even when the input voltage V IN changes rapidly in the increasing direction. As described above, the conventional V-F conversion circuit has a problem that the V-F conversion function does not work sufficiently for a sudden change in the input voltage.
本考案は、前記のような従来のＶ−Ｆ変換回路の問題点
を除去するためになされたもので、その目的とするとこ
ろは、低い発振周波数を得ると共に入力電圧VINの急激
な変化に対しても追従性が良く、周波数変換が効率良く
行なわれるＶ−Ｆ変換回路を提供することにある。The present invention has been made in order to eliminate the above-mentioned problems of the conventional VF conversion circuit. The purpose of the present invention is to obtain a low oscillation frequency and to prevent a sudden change in the input voltage V IN. Another object of the present invention is to provide a V-F conversion circuit that has good followability and can perform frequency conversion efficiently.
上記目的を達成するため本考案により成された電圧−周
波数変換回路は、演算増幅器１と、該演算増幅器の反転
入力端子に一端が、出力端子に他端がそれぞれ接続され
た積分用コンデンサC1と、該積分用コンデンサC1の一端
に接続され入力電圧VINによる充電電流を前記積分用コ
ンデンサC1に供給する充電用抵抗R1と、前記入力電圧V
INを分圧した基準電圧を前記演算増幅器の非反転入力端
子に供給する抵抗R3及びR4とを有し、前記積分用コンデ
ンサC1が前記基準電圧以上に充電されると前記演算増幅
器１の出力が反転する積分回路Ａと、前記積分回路Ａの
出力が反転入力端子に接続された演算増幅器２と、該演
算増幅器２の非反転端子に比較電位を与える手段R7及び
R8と、比較電位を演算増幅器２の出力に応じて変化させ
てヒステリシスを与える手段R6とを有し、反転入力端子
の電圧が非反転入力端子より小さくなると出力が反転す
るコンパレータＢと、前記コンパレータＢの出力により
オン・オフ制御されるスイッチング手段３と、該スイッ
チング手段３と前記積分用コンデンサC1の一端との間に
制御された放電用抵抗R2とを有し、前記スイッチング手
段３のオンにより前記積分用コンデンサC1の充電電荷を
放電させる放電回路Ｃとを備え、前記抵抗R4と並列にコ
ンデンサC2を接続すると共に、前記コンデンサC2の前記
抵抗R3を通じての充電時定数及び前記抵抗R4を通じての
放電時定数を、前記積分用コンデンサC1の抵抗R1を通じ
ての充電時定数及び抵抗R2を通じての放電時定数とにそ
れぞれ略等しくして、前記基準電圧が入力電圧VINに追
従して変化するようにしたことを特徴としている。To achieve the above object, a voltage-frequency conversion circuit according to the present invention comprises an operational amplifier 1 and an integrating capacitor C 1 having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal. When a charging resistor R 1 supplies the charging current to the integrating capacitor C 1 by the input voltage V iN is connected to one end of the integrating capacitor C 1, the input voltage V
The operational amplifier 1 has resistors R 3 and R 4 for supplying a reference voltage obtained by dividing IN to the non-inverting input terminal of the operational amplifier, and when the integrating capacitor C 1 is charged to the reference voltage or more. Of the output of the integrator A, an operational amplifier 2 having the output of the integrator A connected to an inverting input terminal, a means R 7 for applying a comparison potential to the non-inverting terminal of the operational amplifier 2.
And R 8, is changed according to comparison potential to the output of the operational amplifier 2 and means R 6 to give hysteresis, a comparator B output voltage of the inverting input terminal is smaller than the non-inverting input terminal is inverted, The switching means 3 is on / off controlled by the output of the comparator B, and the controlled discharging resistor R 2 is provided between the switching means 3 and one end of the integrating capacitor C 1. the third on a discharge circuit C for discharging the electric charge of the integrating capacitor C 1, together with a capacitor C 2 in parallel with the resistor R 4, charging through the resistor R 3 of the capacitor C 2 the discharge time constant through constant and the resistor R 4 when, substantially equal respectively to the discharge time constant through the charging time constant and the resistance R 2 through resistor R 1 of the integrating capacitor C 1 It is characterized in that the reference voltage is so varied as to follow the input voltage V IN.
本考案のＶ−Ｆ変換回路は、積分回路Ａの基準電圧V1 +
を設定する抵抗R3，R4の抵抗R4と並列にコンデンサC2を
付加することにより、入力電圧VINの変化による基準電
圧V1 +の電位変化の時定数を、コンデンサC1の充放電時
の時定数と等しくするようにしたので、入力電圧VINの
急激な変化に対しても出力電圧波形の追従性を改善する
ことができるものである。The VF conversion circuit of the present invention uses the reference voltage V 1 + of the integration circuit A.
By adding a capacitor C 2 in parallel with the resistor R 4 of the resistors R 3 and R 4 for setting, the time constant of the potential change of the reference voltage V 1 + due to the change of the input voltage V IN can be determined by charging the capacitor C 1 . Since it is made equal to the time constant at the time of discharging, it is possible to improve the followability of the output voltage waveform even with a sudden change in the input voltage V IN .
以下、本考案の実施例を第１図及び第２図と共に説明す
る。なお、前記した従来例と同一符号は同一部分を示し
説明は省略する。本考案にあっては、第３図の積分回路
Ａの演算増幅器１の非反転入力端子の基準電圧V1 +の印
加部を構成する抵抗R4に並列にコンデンサC2を付加した
ことを特徴とするものである（第１図の点線部分）。Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The same reference numerals as those in the conventional example described above indicate the same parts, and a description thereof will be omitted. The present invention is characterized in that a capacitor C 2 is added in parallel with a resistor R 4 which constitutes a portion for applying a reference voltage V 1 + of a non-inverting input terminal of an operational amplifier 1 of an integrating circuit A shown in FIG. (Dotted line part in FIG. 1).
而して、動作について説明するに、例えば第２図におい
て入力電圧VINが急激に減少した時（t3を示す）、積分
回路Ａの基準電圧V1 +は抵抗R4に並列に付加されたコン
デンサC2の効果により、τ１＝C2・R4の時定数で電位が
変化する。このため、時定数τ１をコンデンサC1の充放
電時定数と等しく設定すればVINの変化に追従してＶ−
Ｆ変換動作が行なわれる。また、VINが急激に増加する
時には、τ２＝C2・R3・R4／（R3＋R4）の時定数にて同
様な動作が得られる。第２図（ａ）の入力電圧VINの急
激な変化に対し、出力電圧波形が改善されている状態を
（ｂ）に示す。Thus, to explain the operation, for example, when the input voltage V IN sharply decreases (indicates t 3 ) in FIG. 2, the reference voltage V 1 + of the integrating circuit A is added in parallel to the resistor R 4. Due to the effect of the capacitor C 2 , the potential changes with the time constant of τ 1 = C 2 · R 4 . Therefore, if the time constant τ 1 is set to be equal to the charging / discharging time constant of the capacitor C 1 , the change in V IN follows V −
The F conversion operation is performed. Further, when V IN increases rapidly, similar operation can be obtained with a time constant of τ 2 = C 2 · R 3 · R 4 / (R 3 + R 4 ). FIG. 2B shows a state in which the output voltage waveform is improved with respect to the abrupt change of the input voltage V IN in FIG. 2A.
以上説明したように、入力電圧VINの変化による基準電
圧V1 +の電位変化の時定数を、コンデンサC1の充放電時
定数と等しくするよう構成したので、入力電圧の急激な
変化に対応ての、安定な出力波形が得られるため積分回
路の時定数を大きく設定でき、低い発振周波数を得るこ
とができる。As described above, since the time constant of the potential change of the reference voltage V 1 + due to the change of the input voltage V IN is configured to be equal to the charge / discharge time constant of the capacitor C 1 , it is possible to cope with a sudden change of the input voltage. Since a stable output waveform can be obtained, the time constant of the integrating circuit can be set large and a low oscillation frequency can be obtained.
第１図は本考案の電圧−周波数変換回路の実施例を示す
電気回路図、 第２図は同上の動作説明用信号波形図、 第３図は従来の電圧−周波数変換回路の一例を示す電気
回路図、 第４図は同上の動作説明用信号波形図である。 Ａ…積分回路、Ｂ…コンパレータ、Ｃ…放電回路、1,2
…演算増幅器、C1，C2…コンデンサ、R1〜R4，R6〜R8…
抵抗、３…スイッチング手段（トランジスタ）。FIG. 1 is an electric circuit diagram showing an embodiment of a voltage-frequency conversion circuit of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the same as above, and FIG. 3 is an electric circuit showing an example of a conventional voltage-frequency conversion circuit. A circuit diagram and FIG. 4 are signal waveform diagrams for explaining the same as above. A ... Integrator circuit, B ... Comparator, C ... Discharge circuit, 1, 2
… Operational amplifier, C 1 , C 2 … Capacitor, R 1 to R 4 , R 6 to R 8 …
Resistance, 3 ... Switching means (transistor).
Claims (1)
端子に一端が、出力端子に他端がそれぞれ接続された積
分用コンデンサC1と、該積分用コンデンサC1の一端に接
続され入力電圧VINによる充電電流を前記積分用コンデ
ンサC1に供給する充電用抵抗R1と、前記入力電圧VINを
分圧した基準電圧を前記演算増幅器の非反転入力端子に
供給する抵抗R3及びR4とを有し、前記積分用コンデンサ
C1が前記基準電圧以上に充電されると前記演算増幅器１
の出力が反転する積分回路Ａと、 前記積分回路Ａの出力が反転入力端子に接続された演算
増幅器２と、該演算増幅器２の非反転端子に比較電位を
与える手段R7及びR8と、比較電位を演算増幅器２の出力
に応じて変化させてヒステリシスを与える手段R6とを有
し、反転入力端子の電圧が非反転入力端子より小さくな
ると出力が反転するコンパレータＢと、 前記コンパレータＢの出力によりオン・オフ制御される
スイッチング手段３と、該スイッチング手段３と前記積
分用コンデンサC1の一端との間に制御された放電用抵抗
R2とを有し、前記スイッチング手段３のオンにより前記
積分用コンデンサC1の充電電荷を放電させる放電回路Ｃ
とを備え、 前記抵抗R4と並列にコンデンサC2を接続すると共に、前
記コンデンサC2の前記抵抗R3を通じての充電時定数及び
前記抵抗R4を通じての放電時定数を、前記積分用コンデ
ンサC1の抵抗R1を通じての充電時定数及び抵抗R2を通じ
ての放電時定数とにそれぞれ略等しくして、前記基準電
圧が入力電圧VINに追従して変化するようにした ことを特徴とする電圧−周波数変換回路。1. An operational amplifier 1 , an integrating capacitor C 1 having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal, and an input connected to one end of the integrating capacitor C 1. a charging resistor R 1 supplies the charging current to the integrating capacitor C 1 by the voltage V iN, the non-inverting resistors R 3 and supplied to the input terminal of the dividing reference voltage the input voltage V iN the operational amplifier R 4 and the integration capacitor
When C 1 is charged above the reference voltage, the operational amplifier 1
An integrator circuit A for inverting the output of the operational amplifier, an operational amplifier 2 whose output is connected to the inverting input terminal, and means R 7 and R 8 for applying a comparison potential to the non-inverting terminal of the operational amplifier 2. A comparator B which has a means R 6 for giving a hysteresis by changing the comparison potential according to the output of the operational amplifier 2 and which inverts the output when the voltage of the inverting input terminal becomes smaller than the non-inverting input terminal; Switching means 3 which is on / off controlled by an output, and a discharge resistance controlled between the switching means 3 and one end of the integrating capacitor C 1.
R 2 and a discharge circuit C for discharging the charge stored in the integrating capacitor C 1 when the switching means 3 is turned on.
And a capacitor C 2 is connected in parallel with the resistor R 4, and the charging time constant of the capacitor C 2 through the resistor R 3 and the discharging time constant of the capacitor C 2 through the resistor R 4 are A voltage characterized by making the reference voltage change following the input voltage V IN by making the charging time constant through the resistor R 1 and the discharging time constant through the resistor R 2 of 1 respectively. -Frequency conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14119488U JPH0728736Y2 (en) | 1988-10-31 | 1988-10-31 | Voltage-frequency conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14119488U JPH0728736Y2 (en) | 1988-10-31 | 1988-10-31 | Voltage-frequency conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0262819U JPH0262819U (en) | 1990-05-10 |
| JPH0728736Y2 true JPH0728736Y2 (en) | 1995-06-28 |
Family
ID=31406050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14119488U Expired - Lifetime JPH0728736Y2 (en) | 1988-10-31 | 1988-10-31 | Voltage-frequency conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0728736Y2 (en) |
-
1988
- 1988-10-31 JP JP14119488U patent/JPH0728736Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0262819U (en) | 1990-05-10 |
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