JPS58130653A - Duplex type data transmitter - Google Patents

Duplex type data transmitter

Info

Publication number
JPS58130653A
JPS58130653A JP57196857A JP19685782A JPS58130653A JP S58130653 A JPS58130653 A JP S58130653A JP 57196857 A JP57196857 A JP 57196857A JP 19685782 A JP19685782 A JP 19685782A JP S58130653 A JPS58130653 A JP S58130653A
Authority
JP
Japan
Prior art keywords
signal
clock
slave station
station
master station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57196857A
Other languages
Japanese (ja)
Inventor
エドガ−ル・バ−デル
ゲルト・ロ−ルバツハ
ユルゲン・ペ−テルゼン
ル−トヴイツヒ・キツテル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tekade Felten and Guilleaume Fernmeldeanlagen GmbH
Original Assignee
Tekade Felten and Guilleaume Fernmeldeanlagen GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tekade Felten and Guilleaume Fernmeldeanlagen GmbH filed Critical Tekade Felten and Guilleaume Fernmeldeanlagen GmbH
Publication of JPS58130653A publication Critical patent/JPS58130653A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1423—Two-way operation using the same type of signal, i.e. duplex for simultaneous baseband signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 発明の関連する技術分野 親局と子局との間で２線回線を介してデュゾレツクス方
式で伝送を行うデータ伝送装置〒あって、親局において
第１のクロック周期をもつｆｊ　号ステップクロックが
発生され、このクロック周期の前半に親局から子局へと
信号が伝送され、後事において子局から親局へと信号が
伝送され、また信号伝送符号として、子局からの送信信
号を親局の信号ステップクロックと同期〒きるように選
定されている符号を使用したデュゾレツクス方式のデー
タ伝送装置に関する。[Detailed Description of the Invention] Technical field to which the invention pertains There is a data transmission device that performs transmission between a master station and a slave station via a two-wire line using the Duzorex method, the master station having a first clock period. fj step clock is generated, a signal is transmitted from the master station to the slave station in the first half of this clock cycle, a signal is transmitted from the slave station to the master station later, and a signal is transmitted from the slave station as a signal transmission code. The present invention relates to a Dusolex data transmission device using a code selected to synchronize a transmission signal from a master station with a signal step clock of a master station.

公知技術 。この公知の装置は近距離間の短い伝搬時間でのイ」号
伝送用である。２線同線上で、親局がらｒ局へと、また
はその逆へと伝送方向転換が交ｔ７に迅速に行なわれ、
そのつど単に１つの信号ステップに古まれる信号（１ビ
ツト、１双ビツト、１トライビツト）のみ伝送される。Known technology. This known device is for the transmission of digital signals over short distances and short propagation times. On the same line as the two lines, the transmission direction is quickly changed from the master station to the r station or vice versa at the intersection t7,
Only signals (1 bit, 1 double bit, 1 tri bit) that are reduced to only one signal step each time are transmitted.

伝送コードは、子局から信号ステップクロックが導出さ
れるように選定されており、これにより子局が親局と同
期される。The transmission code is selected such that a signal step clock is derived from the slave station, thereby synchronizing the slave station with the master station.

この公知の装置フは子局に能動的クロック発生器が設け
られていない。従って回線が遮断されたときは、子局に
接続された端末機が子局からクロックを受けとれない。In this known device, the slave station is not provided with an active clock generator. Therefore, when the line is cut off, the terminal connected to the slave station cannot receive the clock from the slave station.

また前記公知の装置の場合、親局から子局へはノ々イポ
ーラＲＺ（リタンツーゼロ）１号が送られ、子局から親
局へはユニポーラＲＺ（！Ｊタンツーゼロ）信号が送ら
れる。両送倍信号は各々ＮＲＺ　（ノンリタンツーゼロ
）信号から成るクロックにより制御されて再生される。Further, in the case of the known device, a non-polar RZ (return to zero) No. 1 signal is sent from the master station to the slave station, and a unipolar RZ (!J tan to zero) signal is sent from the slave station to the master station. Both multiplied signals are controlled and reproduced by clocks each consisting of an NRZ (non-return-to-zero) signal.

しかし直流分のない伝送は先のＲＺ倍信号は行なえない
。However, the RZ multiplied signal cannot be transmitted without a DC component.

発明の目的 本発明の目的は、子局が親局のクロックに依存しないク
ロックを発生し、子局のクロック周期が受信時に迅速に
親局のクロック周期と同期される、冒頭に述べた形式の
装置を提供することにある。OBJECTS OF THE INVENTION The object of the invention is to provide a system of the type mentioned at the outset, in which the slave station generates a clock independent of the clock of the master station, and the clock period of the slave station is rapidly synchronized with the clock period of the master station upon reception. The goal is to provide equipment.

発明の構成と効果 この目的は、特許請求の範囲記載の本発明の構成により
達成される。子局において能動的にクロック発生を行う
ことによって、子局と接続された端末機が子局により常
にクロック制御されるようになる。その際、受信時には
親局の送ｆ、（クロックと同期されたクロックで制御が
行われ、伝送区間の遮断時には、親局のクロックとは異
なるクロック〒制御が行なわれ、しかもこの異なるクロ
ックが受信時に迅速に親局のクロックに同期されるよう
になる。Structure and Effects of the Invention This object is achieved by the structure of the present invention as described in the claims. By actively generating a clock in the slave station, the terminal connected to the slave station is always under clock control by the slave station. At that time, during reception, control is performed using a clock that is synchronized with the transmission clock of the master station, and when the transmission section is interrupted, a clock that is different from the clock of the master station is controlled, and this different clock is used for reception. The clock can be quickly synchronized with the master station's clock.

本発明の有利な実施例が実施態様項記載の構成により実
現される。Advantageous embodiments of the invention are realized by the features described in the implementation section.

次に本発明の実施例を図面を用いて詳細に説明する。Next, embodiments of the present invention will be described in detail using the drawings.

第１図のデータ伝送装置のブロック回路図において、端
末機］は親局２に、別の端末機３は子局４に接続されて
いる。この場合、端末機とは例えばテレックス装置のこ
とである。親局２は２線回線５を介して子局４に接続さ
れており、この２９回線は短く、例えば１つの建物内に
布設される。In the block circuit diagram of the data transmission apparatus shown in FIG. 1, one terminal is connected to a master station 2, and another terminal 3 is connected to a slave station 4. In this case, the terminal is, for example, a telex device. The master station 2 is connected to the slave station 4 via a two-line line 5, and these 29 lines are short and are installed within one building, for example.

親局２は、水晶発振ＷＱＩにより制御されるクロック発
生器Ｔ１を有し、このクロック発生器は送信クロックａ
（第２図ａ）を一方ではコーグＣ１に他方ではデコーダ
Ｄ１に供給する。The master station 2 has a clock generator T1 controlled by a crystal oscillation WQI, and this clock generator is a transmission clock a
(FIG. 2a) on the one hand to Korg C1 and on the other hand to decoder D1.

コーグＣ１は端末機１から送信データｂ（第２図ｂ）を
受けとり、このデータを送信信号Ｃ（第２図Ｃ）にフー
ド化して、２線回線５に接続された変成器Ｕ１に供給す
る。変成器ＵｌはデコーダＤＩにも接続されており、デ
コーダは端末機１に受信データを供給する。Korg C1 receives the transmission data b (FIG. 2b) from the terminal 1, converts this data into a transmission signal C (FIG. 2C), and supplies it to the transformer U1 connected to the two-wire line 5. . The transformer Ul is also connected to a decoder DI, which supplies the terminal 1 with received data.

子局４はコーグ０２を有し、このコーグも端末機３から
の送信データをコーグＣ１と同様に送信信号１（第２図
１）に変換し、この信号を２線回線５に接続された変成
器Ｕ２に供給する。子局４には、例えば４．６ＭＨｚの
定格周波数で動作する水晶発振器Ｑ２が設けられている
。水晶発振器Ｑ２は、分局器を備えたクロック発生器Ｔ
２に接続されており、分周器は入力端６で分周比をｎ−
１とｎ＋１との間で切換え可能〒あり、出力側７には受
信クロックｈが送出される。なおｎは発振器Ｑ２の周波
数と受信クロッりｈの周波数との比を表わす。受信クロ
ックｈはイン・ζ−タエにより反転された後、送信クロ
ックｇとしてコーグＣ２に供給される。The slave station 4 has a Korg 02, and this Korg also converts the transmission data from the terminal 3 into a transmission signal 1 (Fig. 2, 1) in the same way as the Korg C1, and this signal is connected to the 2-line line 5. Supplies transformer U2. The slave station 4 is provided with a crystal oscillator Q2 that operates at a rated frequency of, for example, 4.6 MHz. The crystal oscillator Q2 is a clock generator T equipped with a divider.
2, and the frequency divider divides the frequency division ratio at input 6 to n-
It is switchable between 1 and n+1, and the reception clock h is sent to the output 7. Note that n represents the ratio between the frequency of the oscillator Q2 and the frequency of the received clock h. After the reception clock h is inverted by the inverter, it is supplied to the Korg C2 as the transmission clock g.

ｆ局４は２つのコンノミレータＫＯＭＰＩおよびＫＯＭ
Ｐ２を備え、これらに変成器Ｕ２が接続されている。一
方のコン・ξレータでは受信信号ｄの正の成分が、他方
のコンノミレータでは負の成分が整流され且つ振幅制限
される。各フン・ξレータには微分回路り工Ｆ１ないし
Ｄ工Ｆ２が後置ｆ＆ｆｉされており、微分回路の出力・
ξルスはＡＮＤゲート８を介して相反に結合される。Ａ
ＮＤゲート８従ってＡＮＤゲート８の出力側には信号ｅ
が生じ、パルス信号θは受信信号ｄの零通過時点で発生
する。この零点通過信号θは位相比較回路９の一方の入
力端に加えられ、位相比較回路９の他方の入力端には、
分周器の出力側７の受信クロックｈを遅延素子１０を介
して遅延して取出される基準クロックｆが加えられる。f station 4 has two connomitors KOMPI and KOM
P2, and a transformer U2 is connected to these. One connominator rectifies and limits the amplitude of the positive component of the received signal d, and the other connomitor rectifies and limits the amplitude of the negative component. Differential circuit circuit F1 or D circuit F2 is postfixed to each function/ξlator, and the output of the differential circuit is
The ξ ruses are reciprocally coupled via an AND gate 8. A
ND gate 8 Therefore, the output side of AND gate 8 receives signal e.
occurs, and the pulse signal θ is generated when the received signal d passes through zero. This zero point passing signal θ is applied to one input terminal of the phase comparison circuit 9, and the other input terminal of the phase comparison circuit 9 is
A reference clock f, which is extracted by delaying the received clock h at the output side 7 of the frequency divider via a delay element 10, is added.

位相比較回路９の出力側は分周器の入力端６に接続され
ており、信号θとｆとが時間的にオーツ９−ラップしな
いとき、または受信信号ｄが全く加わっていないとき、
分周比がｎ＋１となるよう分局器を制御する。信号θと
ｆとがオー・ｙ−ラップすれは分周比はｎ−１に切換え
られる。The output side of the phase comparison circuit 9 is connected to the input terminal 6 of the frequency divider, and when the signals θ and f do not overlap in time or when the received signal d is not added at all,
The divider is controlled so that the frequency division ratio becomes n+1. When the signals θ and f overlap by Y-, the frequency division ratio is switched to n-1.

出力側７は端末機３のクロック入力端と接続されている
。コンパレータＫＯＭＰ２は、出力側７から別の遅延素
子１１を介して制御される再生器（スカナ）１２と共に
子局のデコーダＤ２を構成している。再生値はフリップ
フロップ１３に加えられ、そこから受信データとして端
末機に供給される。フリップ７０ツゾ１３は受信クロッ
クｈによって制御される。The output side 7 is connected to the clock input terminal of the terminal 3. The comparator KOMP2 together with a regenerator (scanner) 12 which is controlled from the output side 7 via a further delay element 11 constitutes a decoder D2 of the slave station. The reproduced value is applied to a flip-flop 13, from which it is supplied to the terminal as received data. The flip 70 and the clock 13 are controlled by the receive clock h.

次に上記装置の動作を説明する。Next, the operation of the above device will be explained.

送信クロックａはクロック周期Ｔａを有し、衝撃係数５
０％１ある。送信クロックａが１１“信号の間、コーグ
Ｃ１は動作し、デコーダＤ１は遮断される。１０′信号
の間、コーグＣ１は遮断され、デコーダＤ１は動作する
。The transmission clock a has a clock period Ta and has an impact coefficient of 5
There is 0%1. During the 11'' signal of the transmission clock a, the Korg C1 operates and the decoder D1 is shut off. During the 10' signal, the Korg C1 is shut off and the decoder D1 operates.

第２図ａ〜１は第１図の回路の波形図を示し、送信デー
タｂに対し例えばノンリタンラーゼｔ−ｔ（ＮＲＺ）信
号ゝ０“　％（１“、′１“　ＳＳ　６“、“１“が示
されている。この送信データｂはクロックｄが１“信号
の間コーグＣ１で、直流成分のない送ｆｉｊ信号Ｃに変
換される。つまり各送信信号単位が、各１つの負の信号
成分と正の信号成分とから成っており、その際１０“信
号は先ず負、次に正の成分という構成にされ、′Ｘ１“
信号は先ず正、次に負の成分という構成にされている（
第２図Ｃ）。FIGS. 2a to 1 show waveform diagrams of the circuit in FIG. 1" is shown. This transmission data b is converted into a transmission fij signal C without a DC component by the Cog C1 while the clock d is a 1" signal.In other words, each transmission signal unit has one negative It consists of a signal component and a positive signal component, in which case the 10" signal is structured first as a negative component and then as a positive component, and 'X1"
The signal consists of positive components first, then negative components (
Figure 2C).

送イ４信号Ｃは２線回線５を伝送された後に受信信号ｄ
として現われる。この受信信号ｄがら、受信信号ｄの零
点通過信号ｅが導出される。The transmitted signal C is transmitted through the 2-line line 5, and then the received signal d
appears as. A zero point passing signal e of the received signal d is derived from the received signal d.

零点通過信号θは送信クロックａのクロック・ξルス周
期Ｔａで生じる。このクロック周期Ｔａに、受信クロッ
クｈのクロック周期Ｔｈを同期させる必要がある。この
ために、発振器Ｑ２ないしクロック発生ａＴ２から遅延
素子１０を介して導出される基準クロックｆの立下がり
縁の位相が、零点通過信号θの立上り縁の位相と比較さ
れる。零点通過信号ｅの立上り縁は、送信クロックａの
立上り縁に対し、クロック周期Ｔａ０４分の１だけ遅延
している。この点を考慮するために、零通過信号ｅとの
比較により評価される基準クロックｆの立下がり縁も、
遅延素子１０によって同じ時間だけ遅延させる。信号ｆ
が信号ｅとオー、Ｓラップすると、分周器が分周比ｎ　
−１、（”は例えば３８４〒ある）に切換えられる。信
号ｅが信号ｆとオー・ぐ−ラップしないとき、分周比が
ｎ＋１に切換えられる。これにより、基準クロックｆの
立下がり縁と零点通過信号θの立上がり縁との間だけジ
ッタが生する。つまり子局４の出力側７のクロックが親
局２の送信クロックに捕捉される。送信クロックｇは受
信クロックｈに、ひいては送信クロックａに対して反転
させられるので、端末機３の送信データから導出される
送信信号１（この実施例では１１“　ＳＳ　□“　％Ｓ
　ｏ“、“　“、５１“）は、コーグｃ１が遮断されデ
コーダＤ１が動作して　　　゛いるときに伝送される。The zero point passing signal θ is generated at the clock ξ pulse period Ta of the transmission clock a. It is necessary to synchronize the clock period Th of the reception clock h with this clock period Ta. For this purpose, the phase of the falling edge of the reference clock f derived from the oscillator Q2 or the clock generator aT2 via the delay element 10 is compared with the phase of the rising edge of the zero-crossing signal θ. The rising edge of the zero point passing signal e is delayed by one quarter of the clock period Ta0 with respect to the rising edge of the transmission clock a. In order to take this point into account, the falling edge of the reference clock f evaluated by comparison with the zero crossing signal e is also
The delay element 10 delays the same amount of time. signal f
When O, S wraps with the signal e, the frequency divider has the division ratio n
-1, (" is 384, for example). When the signal e does not overlap with the signal f, the division ratio is switched to n+1. This causes the falling edge and zero point of the reference clock f to Jitter occurs only between the rising edge of the passing signal θ.In other words, the clock at the output side 7 of the slave station 4 is captured by the transmission clock of the master station 2.The transmission clock g is captured by the reception clock h, and by extension the transmission clock a. Since the transmission signal 1 derived from the transmission data of the terminal 3 (in this example, 11" SS □" %S
o", "", 51") are transmitted when the cog c1 is cut off and the decoder D1 is operating.

回線によって生じる伝搬時間については、クロック周期
に比べて問題にならないほど短い時間なので、ここでは
詳しく図示しなかった。The propagation time caused by the line is not shown in detail here because it is too short to be a problem compared to the clock cycle.

遅延素子１】は受信クロックｈをパルス繰返し周期Ｔｈ
の８分の３だけ遅延させる。これにより再生器１２にお
いて最良の再生走査が行なオー）れるようになる。最良
の再生走査とは、比較的大きいさん孔で再生走査が行な
われるということを意味する。Delay element 1] converts the received clock h into a pulse repetition period Th
delay by three-eighths. This allows the regenerator 12 to perform the best regeneration scan. The best regeneration scan means that the regeneration scan is performed with a relatively large borehole.

二Ｆ局４が受信信号ｄを受信しない限り、分周器は分周
比ｎ＋］〒動作する。この間・ξルス周期Ｔｈは・？ル
ス周期Ｔａに対して比較的大きくずれている。従って受
信信号ｅが到来すると間もなく基準クロックｆの立下が
り縁が、零点通過信号θの立」二かり縁と一致する時点
に達する。これにより所望の同期が行なわれる。As long as the second F station 4 does not receive the received signal d, the frequency divider operates at a frequency division ratio n+]. What is the ξrus period Th during this time? There is a relatively large deviation from the pulse period Ta. Therefore, soon after the reception signal e arrives, the falling edge of the reference clock f reaches a point where it coincides with the rising edge of the zero point passing signal θ. This provides the desired synchronization.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のデー・全伝送装置のブロック回路図、
第２図ａ〜１は第１図の装置の信号の１侍間に関する波
形図１ある。 ２・・親局、４・・・子局、７．ｈ・・・子局クロック
、Ｔ２・・・クロック発生器 手続補正書（方式） 昭和５８年３月１８　　日 ４１＋ｌｉ’ｌ庁長官殿 １　市１′１の表示昭和５７年特許願第１９６８５７号
２　発明の名称 デュゾレノクス方式データ伝送装置 ３　補［［、をする者 軒はの関係：特許出願人 ハフラング ４復代理人 昭和５８年　２月２２日　　（発送日）３０３−FIG. 1 is a block circuit diagram of the data/all transmission device of the present invention.
FIGS. 2a-1 are waveform diagrams 1 for each signal of the apparatus of FIG. 1. 2... Master station, 4... Slave station, 7. h...Slave station clock, T2...Clock generator procedure amendment (method) March 18, 1980 41+li'l Director-General 1 City 1'1 Display 1988 Patent Application No. 196857 2 Name of the invention Duzolenox data transmission device 3 Supplementary relationship: Patent applicant Haffrang 4 sub-agent February 22, 1983 (Date of dispatch) 303-

Claims (1)

【特許請求の範囲】 ｒ　＆局において第１のクロック周期をもつ信はスアツ
ゾクロックが発生され、このクロック周期の前半に親局
から子局へと信号が伝送され、後半において子局から親
局へと信号が伝送され、また信号伝送符号としては、子
局からの送信信号を信号ステップクロックと同期できる
ように選定された符号を使用した、親局と子局との間で
２線回線を介してデュプレックス方式！伝送を行うデー
タ伝送装置において、子局に自動切換ｇ１能なりロック
発生器（Ｑ　２　、　Ｔ　２　）を設け、該クロック発
生器の発生する子局タロツク信号（ｈ）の第２のり「Ｊ
ツク周期（Ｔｈ）が、第１の親局のクロック周期（Ｔ’
ａ）に同期されない間は、第１のクロック周期から所定
の値だけずれているようにし、史に第１のクロック周期
と第２のクロック周期とを比較する位相比較回路（９）
を設け、該位相比較回路が切換可能なりロック発生器（
Ｔ２）を制御するようにしたことを特徴とする、デュゾ
レツクス方式のデータ伝送装置。 ２　クロック発生器（Ｔ２）に分周器を設け、該分周器
が位相比較回路（９）によって、分周比ｎ＋１から分周
比ｎ−１へと切換えられるようにした特許請求の範囲第
１項記載のデータ伝送装置。 ３　位相比較回路（９）が、受信信号（ｄ）の零点通過
の位相を、クロック発生器（Ｔ２）のクロック信号の位
相と比較するようにした特許請求の範囲第１項または第
２項記載のデータ伝送装置。[Claims] In the r & station, a signal having a first clock period is generated by a suatsuzo clock, and in the first half of this clock period, the signal is transmitted from the master station to the slave station, and in the second half, the signal is transmitted from the slave station to the master station. The signal is transmitted between the master station and the slave station via a two-wire line, using a code selected to synchronize the transmitted signal from the slave station with the signal step clock as the signal transmission code. Duplex style! In a data transmission device that performs transmission, a slave station is provided with an automatic switching g1 lock generator (Q 2 , T 2 ), and a second signal "J" of the slave station tarlock signal (h) generated by the clock generator is provided.
The clock cycle (Th) is equal to the clock cycle (T') of the first master station.
a) A phase comparator circuit (9) that deviates from the first clock cycle by a predetermined value while it is not synchronized with the clock cycle, and then compares the first clock cycle and the second clock cycle.
The phase comparison circuit is switchable and a lock generator (
1. A Duzorex type data transmission device, characterized in that it controls T2). 2. The clock generator (T2) is provided with a frequency divider, and the frequency divider is switched from the frequency division ratio n+1 to the frequency division ratio n-1 by the phase comparator circuit (9). The data transmission device according to item 1. 3. Claim 1 or 2, wherein the phase comparison circuit (9) compares the phase of the received signal (d) passing through a zero point with the phase of the clock signal of the clock generator (T2). data transmission equipment.
JP57196857A 1981-11-13 1982-11-11 Duplex type data transmitter Pending JPS58130653A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19813145126 DE3145126A1 (en) 1981-11-13 1981-11-13 DATA TRANSFER SYSTEM FOR FULL DUPLEX TRANSFER
DE31451268 1981-11-13

Publications (1)

Publication Number Publication Date
JPS58130653A true JPS58130653A (en) 1983-08-04

Family

ID=6146319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57196857A Pending JPS58130653A (en) 1981-11-13 1982-11-11 Duplex type data transmitter

Country Status (4)

Country Link
EP (1) EP0079527B1 (en)
JP (1) JPS58130653A (en)
CA (1) CA1196407A (en)
DE (2) DE3145126A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4823364A (en) * 1987-03-12 1989-04-18 The Boeing Company Receive coupler for binary data communication systems
US4825450A (en) * 1987-03-12 1989-04-25 The Boeing Company Binary data communication system
CA1311033C (en) * 1988-03-19 1992-12-01 Shinji Ohta Circuit for obtaining accurate timing information received signal
GB2536309B (en) 2015-03-09 2017-08-02 Cirrus Logic Int Semiconductor Ltd Low power bidirectional bus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1401436A (en) * 1971-10-14 1975-07-16 Gen Electric Co Ltd Pulse transmission systems
JPS5321963B2 (en) * 1973-11-12 1978-07-06
US3983498A (en) * 1975-11-13 1976-09-28 Motorola, Inc. Digital phase lock loop
GB1566223A (en) * 1978-01-17 1980-04-30 Standard Telephones Cables Ltd Digital duplex transmission system

Also Published As

Publication number Publication date
EP0079527A3 (en) 1983-06-29
CA1196407A (en) 1985-11-05
DE3145126A1 (en) 1983-07-14
EP0079527A2 (en) 1983-05-25
EP0079527B1 (en) 1985-06-26
DE3264446D1 (en) 1985-08-01

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