JPS58127249A - Controlling of data flow rate - Google Patents

Controlling of data flow rate

Info

Publication number
JPS58127249A
JPS58127249A JP57010309A JP1030982A JPS58127249A JP S58127249 A JPS58127249 A JP S58127249A JP 57010309 A JP57010309 A JP 57010309A JP 1030982 A JP1030982 A JP 1030982A JP S58127249 A JPS58127249 A JP S58127249A
Authority
JP
Japan
Prior art keywords
data
identifier
information processing
line
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57010309A
Other languages
Japanese (ja)
Other versions
JPH0363109B2 (en
Inventor
Tsutomu Tenma
天満　勉
Masao Iwashita
岩下　正雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57010309A priority Critical patent/JPS58127249A/en
Priority to EP85110111A priority patent/EP0176712B1/en
Priority to DE8585110111T priority patent/DE3280281D1/en
Priority to EP82109783A priority patent/EP0078034B1/en
Priority to DE8585110112T priority patent/DE3280280D1/en
Priority to US06/436,130 priority patent/US4594653A/en
Priority to EP85110112A priority patent/EP0172522B1/en
Priority to DE8282109783T priority patent/DE3275139D1/en
Publication of JPS58127249A publication Critical patent/JPS58127249A/en
Priority to US06/808,192 priority patent/US4674034A/en
Publication of JPH0363109B2 publication Critical patent/JPH0363109B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent the inflow of data exceeding the processing capacity, by monitoring the difference of the number of transfer rings to transmit and receive data by an identifier, when data comprising an identifier and a data are transmitted and received between two information processors. CONSTITUTION:When a data is transferred to an information processor 2 from an information processor 1, the processor 1 delivers a data comprising an identifier and a data to a line 101 as long as a data acceptable signal exists on a signal line 102 when a cue memory 100 has a data storing area having an FIFO function. This data is preserved at the memory 100 and then read out to a line 103. Then the identifier gives an access to the table memory 100, and a new identifier is read out to a data line 106. An increment monitor bit is applied to a signal line 114. Then a data identifier gives an access to a memory 120 when the data is transferred to the processor 1 from the processor 2 and then delivers a decrement monitor bit to a signal line 113. A counter 130 has an increment or decrement by the signals of signal lines 114 and 113 and then indicates the inhibition of reading through lines 117 and 109 in case the count value is larger than a fixed value of a register 150.

Description

【発明の詳細な説明】 この発明は少なくとも２りの情報処理装置関のデータ授
受を制御するデータ流量制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data flow rate control circuit that controls data exchange between at least two information processing apparatuses.

従来、幾つかのデータフロー慇場装置を＊＊する時、相
互間のデータ授受に余裕を持友せるえめキエーメモリを
介して行なってい友。しかしながら各データフロー処ｍ
ｔ装置でのデータＩＩ＆膳量が異なるため最も処理量の
大きいデータフローｍｉ＋ｕ装置に注目し、他のデータ
フロー処理装置ｏ性能ｔおとして使用するようソフトウ
ェアで制御しなければならなかりえ。Conventionally, when data flow is performed between several devices, it is done through a key memory that allows for ample time for data exchange between them. However, each data flow
Since the data II and the amount of food in the two devices are different, it is necessary to focus on the data flow mi+u device with the largest processing amount and control it with software so that it is used as the other data flow processing devices have the same performance.

本発明の目的はデータフロー処理装置間のデータ授受を
、最も処理量の大きいデータフロー処理装置にあわせて
ソフトウェア制御の助けをか）ず自動的に行なえる回路
を提供することｋるる。SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that can automatically transfer data between data flow processing devices without the aid of software control in accordance with the data flow processing device that has the largest throughput.

例えは、 ｕｉ　ｍｘｉ　＋ｙｉ　Ｘ　ｚゑ（但しｉ　−Ｌ＝−＊
　）　　（１）ｖｉ　Ｍ＝ｘｉ　−ｙｉ　ｘｚｉ として（り式の計算を行なうとき、 情報処理装置ム社ｘｉ、ｙｉ、ｘｉ　　を履次情ＩＩＩ
Ｉ＆場装置Ｂへ過多、情暢処理飯置Ｂ＃′ｉ演算結果ｕ
ｊ　、　ｖｉをデータフロー処珈装置ムに示す。この時
、情報処暑装置ムからＢへは３つのデータ組が単位とし
てａ　ＩＩ　％情報処暑装置Ｂからムへは２つのデータ
ＪＩＳ単位としてｎＦｍ転送される。本発明のデータ流
量制御回路では単位となるデータ組の要素１つ例えば１
通とｖｊＫ着目し、ｘｊが情報Ｊ６１１装置ムからＢへ
送られ丸回数とマｉが情報処暑装置Ｂからムへ送らｔＬ
え１ｉ１数との差の絶対値を時々刻々ｌ視し差の絶対値
がある一定数こえないようにするととてそれぞれの情報
処暑装置での処理能力を超見えデータ流入を防ぐ。又夏
ｉ、ｙｉ、ｇｉの３種のデータには異なつえ識別子例え
ば１０１　、１１１　、　ｅｚｇの値が、舖ｉ　、　ｖ
ｉの２種のデータにも異々り九識別子例えに１ＯＺｌｌ
ｌの値が与えられる。この結果上記例で紘情報魁埋装置
人からＢへの転送データのうち＋２１の値の識別子をも
つデータの転送回数と情報処暑装置Ｂからムへの転送デ
ータのうち＠１１の値の識別子をもつデータの転送回数
とを計数すればよい。For example, ui mxi +yi
) (1) As vi M=xi −yi
Too many to I & field device B, passion processing Iioki B#'i operation result u
j and vi are shown in the data flow processing device. At this time, three data sets are transferred from the information processing device B to the information processing device B as a unit, and nFm are transferred from the information processing device B to the information processing device B as two data JIS units. In the data flow rate control circuit of the present invention, one element of a data set serving as a unit, for example, 1
Focusing on communication and vjK, xj is sent from the information J611 device M to B, and the round number and my i are sent from the information processing device B to M.tL
By checking the absolute value of the difference from the 1i1 number from time to time and making sure that the absolute value of the difference does not exceed a certain number, it is possible to prevent the inflow of data that exceeds the processing capacity of each information processing device. Also, the three types of data for summer i, yi, and gi have different cane identifiers, for example, the values of 101, 111, and ezg, or i, v
The two types of data for i are also different. 9 Identifiers For example, 1OZll
The value of l is given. As a result, in the above example, the number of transfers of data with an identifier of +21 among the data transferred from the information processing device B to B, and the identifier of @11 among the data transferred from the information processing device B to M. It is sufficient to count the number of times the data is transferred.

次にこの発明について図面を参照して説明する。Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す丸めのプロブ（例えば
ＭＭＩ社製Ｃ６７４０１）にデータ格納エリアがある時
、信号線ＩＨにデータ受は入れ可能信号が出力されてい
れば情報処Ｊ１１装置１社データの識別子とデータ値と
からなるデータをデータ線１０１に出力し、キューメモ
リ１００　ｔｉこのデータを一時保存する。キューメモ
ＩＪ１００から一時保存されていえデータがデータ１１
１０３ＫＩＩみ出され、データの識別子がデータＩｗ１
０４を通してテーブルメモリ１１０　ｌアクセスしデー
タ１１１Ｇ６に新しいデータの識別子が銃み出され、信
号線１１４４ｃｊｌｌ加１視ビツトが読み出される・デ
ータ線１０５に４．ｔられるデータ値とデータ＠１０６
に４えらｎ４新しいデータの識別子とが共にデータ９１
０７を通して情報処理装置２に与えられる。情報処理装
置２からデータ＠　１１１を通して入力されえデータ線
そのｔまデータ流１１８１通して情報熟思側１へ与えら
れる。データ９１１Ｂのデータのうちデータの識別子が
データ＠　１１２　を通してメモリ１２０をアクセスし
信号Ｉ／５ＩＩＩＫ減少監視ピット會出力する。カウン
タ１信号紘信号纏１０に増加監視ビットが出力されると
１増加し、信号線１１３　Ｋ減少監視ビットが出力され
ると１減少する。カウンタ１３０の絶対値がデータ線１
１５　Ｋ出力され、レジスタ１５０の出力との大小比較
が比験器１４０で敗られる。データ流１１８　ｔ）値よ
）データ＄９１１５の値が小さい時信号纏１１７　Ｋ　
’１’の値が出力される。情報処暑装置２がデータを受
は塩９可能である時信号纏１０８　Ｋ　’１’の値が出
力され、信号１１１１７　Ｋ　’１”の値が出力されて
いると論理積回路１６０の出力信号線１０９が甲の値を
取る。キューメモリ１００は信号９１０９　Ｋ　”１’
の値が出力されている時睨み出しを続ける。事実施何で
出力部はキューメモリ１００に対応し、出力制御部は破
細で示し九ブロックＢＫ対応する。FIG. 1 shows an embodiment of the present invention when a rounded probe (for example, C67401 manufactured by MMI) has a data storage area, and if a data reception enable signal is output to the signal line IH, the information processing J11 device Data consisting of the identifier and data value of one company data is output to the data line 101, and this data is temporarily stored in the queue memory 100ti. Data temporarily saved from cue memo IJ100 is data 11
103KII is extracted, and the data identifier is data Iw1.
The table memory 110l is accessed through 04, the new data identifier is extracted from the data 111G6, and the signal line 1144cjll is read out. Data value and data @106
4 gills n4 new data identifier and data 91
07 to the information processing device 2. Data is inputted from the information processing device 2 through the data line 111 and is provided to the information contemplation side 1 through the data stream 1181. The data identifier of the data 911B accesses the memory 120 through the data @112 and outputs the signal I/5IIIK decrease monitoring pit. When the increase monitoring bit is output to the counter 1 signal line 10, it increases by 1, and when the decrease monitoring bit is output to the signal line 113, it decreases by 1. The absolute value of counter 130 is data line 1
15K is output, and the comparison with the output of the register 150 is rejected by the comparator 140. Data flow 118 t) value) When the value of data $9115 is small, signal 117 K
A value of '1' is output. When the information processing device 2 is able to receive data, a value of signal 108 K '1' is output, and when a value of signal 11117 K '1' is output, the output signal line of the AND circuit 160 109 takes the value of A.The queue memory 100 receives the signal 9109 K “1”
Continues to stare when the value of is being output. In actuality, the output section corresponds to the queue memory 100, and the output control section corresponds to nine blocks BK, which are shown in phantom.

７７１２図は本発明の伽の実施例を示す丸めのプロ、り
図である。Figure 7712 is a rounding diagram showing an embodiment of the present invention.

−タの授受の制御する潰１示すものである。This figure shows how to control the exchange of data.

情報処珈釦１１から情報処理装置１０に与えるデータが
ある時で流量制御回路２Ｇ−１がデータ線７０−Ｉ　Ｋ
データ受は入れ可能状態を出力している時、情報処暑装
置１１ｑデータの識別子とデータ値とからなるデータを
データ４９５０−２へ出力する。データの識別子線デー
タを区別する丸め与えられ情報処理装置１０で唸この識
別子毎に異なる処１１を行嫌う。データ流５０−２から
入力されるデータは流量制御回路２０−２で識別子に従
う増加監視ビットが付加されデータ線３Ｏ−１ｖｔ通し
て流量制御回路２０−１へ入力されデータが一時保存さ
れる。流量制御回路２０−１で紘データ４９３０−１か
らのデータ入力とデータ流５０−１からのデータ入力を
監視し、情報処理装置１０から信号−＠Ｏ−Ｉ　Ｋデー
タ入力可能状態が出力されている時、一時保存しえデー
タをデータ流４０−１１通して情報処暑装置１０に与え
る。情報ＩＩ＆理装置１Ｇから情報処理装置１１にデー
タを与える場合も同様の手瞑で行なわれる。流量制御回
路２０−１及び２０−２＃ｉ同一の回路で構成される。When there is data to be given to the information processing device 10 from the information processing button 11, the flow rate control circuit 2G-1 connects the data line 70-IK.
When the data receiver is outputting the ready state, it outputs data consisting of the identifier and data value of the information processing device 11q data to the data 4950-2. Identifier line of data The information processing device 10 is given rounding to distinguish the data, and it is difficult to perform different processing 11 for each identifier. The data inputted from the data stream 50-2 is added with an increment monitoring bit according to the identifier by the flow rate control circuit 20-2, and inputted to the flow rate control circuit 20-1 through the data line 3O-1vt, where the data is temporarily stored. The flow rate control circuit 20-1 monitors the data input from the Hiro data 4930-1 and the data input from the data stream 50-1, and the information processing device 10 outputs a signal -@O-I K data input enabled state. When the data is stored, temporarily stored data is provided to the information processing device 10 through the data stream 40-11. The same manual procedure is used when providing data from the information II & processing device 1G to the information processing device 11. The flow rate control circuits 20-1 and 20-2#i are composed of the same circuit.

ＩＩ３図絋滝鉱制御回路２Ｏ−ＩＫついて具体的に示し
えブロック図である・ データ線５０−１からデータが入力されると、デー−の
識別子でテーブルメモリ２０４をアタセスし信号線２５
６に減少監視ビット、信号＠２ＳＩＩＣｊｌｌ加味視ビ
ットを出力し、データ線５Ｇ−１の入力データと信号線
２５！Ｉの増加監視ビットとをデータＩｓ３を通して纂
２１１の流量制御回路２０−２に与える。Fig. II3 is a block diagram specifically showing the control circuit 20-IK. When data is input from the data line 50-1, the table memory 204 is accessed using the data identifier and the signal line 25
6, outputs the decrement monitoring bit and the signal @2SIICjll addition bit, and inputs the input data of the data line 5G-1 and the signal line 25! The increase monitoring bit of I is provided to the flow rate control circuit 20-2 of the chain 211 through data Is3.

信号ｉｌｌ　Ｚ５６の減少監視ビットがＩｌｌの値の時
カクン１２０Ｚ＃ｉｌ減Ｊ）さレル、データ纏３０−Ｉ
　Ｋ入力される第２７ｇの流量制御回路２０−２からの
増加微視ビットとデータはキューメモリ２００に一時保
存される。中ニーメモリ２００　Ｋデータ保持が可能な
時信号線７０−１會通して、ＪＩＩ２図の情報Ｊｌ！＆
瑠装置１１にデータ受は入れ可能状態を出力する。キ。Signal ill When the decrease monitoring bit of Z56 is the value of Ill, it is 120Z#il decrease J), data collection 30-I
The incremental microscopic bits and data input from the 27g flow rate control circuit 20-2 are temporarily stored in the queue memory 200. When the middle knee memory 200K data can be held, the information Jl of the JII2 diagram is passed through the signal line 70-1. &
The device 11 outputs a data reception ready state. tree.

−メモリ２００から読み出されえ増加監視ビットは信号
線２５１【通りてカウンタ２０２　ｌ　１増加させ、デ
ータはデータ線４０−１を通して第２図の情報処理装置
ｉｏに与えられる。- The increment monitoring bit read from the memory 200 passes through the signal line 251 and causes the counter 202 l to increment by 1, and the data is provided to the information processing device io of FIG. 2 through the data line 40-1.

カウンタ２０２の絶対値がデータ線２５７に出力され、
レジスタ２０１の値との大小が比較回路２０３で取られ
る。データ線２５８の値の方がデータ線２５７の値より
大きい時、信号線２５９　Ｋ　’１’の値が出力され、
そうでないときＩ□ｔの値が出力される。The absolute value of the counter 202 is output to the data line 257,
A comparison circuit 203 determines whether the value is greater than or equal to the value in the register 201. When the value of the data line 258 is greater than the value of the data line 257, the value of the signal line 259 K '1' is output,
Otherwise, the value of I□t is output.

９２図の情報処理装置１０かも、信号線６０−１を通し
てデータ入力可能状態が入力され、論履積−路２０５で
信号＠　２５９の値と信号ｌ５６Ｇの値との論理積が取
られ信号＠　２６０　Ｋ出力される。即ち、レジスタ２
０１の値がカウンタ２０２の絶対値よ）大会〈信号＠６
０−１にデータ入力可能状態が出力されている時、信号
１１２６０に’ｌ’の値が出力されキューメモリ２０Ｇ
からのデータの銃与出しが行なわれる。In the information processing device 10 in FIG. 92, the data input enable state is inputted through the signal line 60-1, and the logical product of the value of the signal @ 259 and the value of the signal 156G is taken at the AND path 205, and the value of the signal @ 260 is obtained. K is output. That is, register 2
The value of 01 is the absolute value of the counter 202) Competition〈Signal @6
When the data input enable state is output to 0-1, a value of 'l' is output to the signal 11260 and the queue memory 20G
Data will be transferred from the

なお、レジスタ２０１　、テーブルメモリ２０４にはあ
らかじめ初期データがセットされるが、レジスタ２０１
０代ＤＫ定数発生器、テーブルメモ９２０４としてリー
ドオンリメモリを用いることも可能である。Note that initial data is set in advance in the register 201 and table memory 204;
It is also possible to use a read-only memory as the zero DK constant generator and table memo 9204.

本発明のデータ流量制御回路を用いる仁とＫより２つ以
上の情報処理装置でデータｍａｔ行なう場合、個々の情
報処理装置の処理状態を監視し、互いに処理を同期させ
ソフトウェア制御から解放１詐る。From Jin and K using the data flow rate control circuit of the present invention, when data mating is performed with two or more information processing devices, the processing status of each information processing device is monitored and the processing is synchronized with each other, freeing from software control. .

ｇｗｏ簡単１１１１Ｎ 第１ｍｌは本発明データ流量制御回路の実施例を示すブ
ロック図、菖２図は本発明の４５−りの実施例を示すブ
ロック図、第３図は菖２図の流量制御回路２０．２１の
詳ａｉａｍである０図において、１．λ１０，１１は情
報処理装置、２０゜２１は流量制御回路、　１０Ｇ、Ｚ
ＧＯはキューメモリ、１１０．２０４ｔｉテーブルメモ
リ、１２０はメモリ、１３０．２０２はカウンタ、　１
４０，２０３は比験器、１５０．２０１はレジスタ、　
１６Ｇ、、２０５は論理積回路である。gwo easy 1111N 1st ml is a block diagram showing an embodiment of the data flow rate control circuit of the present invention, Diagram 2 is a block diagram showing a 45th embodiment of the present invention, and Figure 3 is a flow rate control circuit 20 of Diagram 2 In figure 0, which is the detailed aiam of .21, 1. λ10, 11 are information processing devices, 20°21 is a flow rate control circuit, 10G, Z
GO is queue memory, 110.204ti table memory, 120 is memory, 130.202 is counter, 1
40,203 is a comparator, 150.201 is a register,
16G, 205 is an AND circuit.

Claims (1)

【特許請求の範囲】[Claims] 識別子とデータ値とからなるデータｉ′ｉ＃Ｌｐ扱う少
なくとも２つの情報処理装置ＡとＢの間のデータ授受に
おいて、情報処理装置Ａから入力されるデータを保持し
、前記保持データを情報Ｊ６理装置Ｂへ出力するｐ）ｐ
ｏＹｒ含む出力部と、情報処理装置Ｂから情報処理装置
人へ与えられるデータをそのデータの識別子に着目して
計数すると共に、前記出力部から情報処理装置Ｂへ出力
されるデータをそのデータ識別子に着目して計数し、前
記２種類の計数値の差が一定値を超えないように前記出
力部からの出力制御を行なう出力制御部とを備え−ｋｅ
と１＊黴とするデータ流量制御回路〇In data exchange between at least two information processing devices A and B that handle data i'i#Lp consisting of an identifier and a data value, the data input from information processing device A is held, and the held data is processed by information J6. Output to device B p) p
The output section including oYr counts the data given from the information processing device B to the information processing device person by focusing on the identifier of the data, and also calculates the data outputted from the output section to the information processing device B using the data identifier. -ke
and 1* data flow rate control circuit 〇
JP57010309A 1981-10-22 1982-01-26 Controlling of data flow rate Granted JPS58127249A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP57010309A JPS58127249A (en) 1982-01-26 1982-01-26 Controlling of data flow rate
US06/436,130 US4594653A (en) 1981-10-22 1982-10-22 Data processing machine suitable for high-speed processing
DE8585110111T DE3280281D1 (en) 1981-10-22 1982-10-22 DATA PROCESSING SYSTEM WITH MAIN PROCESSOR AND DATA CONTROLLED MODULES.
EP82109783A EP0078034B1 (en) 1981-10-22 1982-10-22 Data processing machine suitable for high-speed processing
DE8585110112T DE3280280D1 (en) 1981-10-22 1982-10-22 DATA PROCESSING DEVICE FOR PROCESSING AT HIGH SPEEDS.
EP85110111A EP0176712B1 (en) 1981-10-22 1982-10-22 Data-processing system comprising a host processor and data-driven modules
EP85110112A EP0172522B1 (en) 1981-10-22 1982-10-22 Data processing machine suitable for high-speed processing
DE8282109783T DE3275139D1 (en) 1981-10-22 1982-10-22 Data processing machine suitable for high-speed processing
US06/808,192 US4674034A (en) 1981-10-22 1985-12-12 Data processing machine suitable for high-speed processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57010309A JPS58127249A (en) 1982-01-26 1982-01-26 Controlling of data flow rate

Publications (2)

Publication Number Publication Date
JPS58127249A true JPS58127249A (en) 1983-07-29
JPH0363109B2 JPH0363109B2 (en) 1991-09-30

Family

ID=11746641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57010309A Granted JPS58127249A (en) 1981-10-22 1982-01-26 Controlling of data flow rate

Country Status (1)

Country Link
JP (1) JPS58127249A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6337457A (en) * 1986-08-01 1988-02-18 Hitachi Ltd Inter-processor data transfer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6337457A (en) * 1986-08-01 1988-02-18 Hitachi Ltd Inter-processor data transfer system

Also Published As

Publication number Publication date
JPH0363109B2 (en) 1991-09-30

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