EP0172522B1 - Data processing machine suitable for high-speed processing - Google Patents
Data processing machine suitable for high-speed processing Download PDFInfo
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- EP0172522B1 EP0172522B1 EP85110112A EP85110112A EP0172522B1 EP 0172522 B1 EP0172522 B1 EP 0172522B1 EP 85110112 A EP85110112 A EP 85110112A EP 85110112 A EP85110112 A EP 85110112A EP 0172522 B1 EP0172522 B1 EP 0172522B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven
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- the present invention relates to a data processing machine according to the preamble of claim 1.
- a pipe line mode has been proposed as an architecture adaptable to a high-speed processing required.
- This mode is based on parallel processing of data and is to control the respective operation flows (i.g., addition processing, subtraction processing, multiplication processiong or division processing) for processing of programs in parallel.
- a processor system employing the pipe line mode is so structured that a plurality of arithmetic circuits each having a fixed single function, such as an adder or multiplier, are connected to each other in a ring form with a bus of the pipe line mode.
- This system is suitable for high-speed processing in that a plurality of operation flows can be executed in parallel.
- the operation system thus structured can produce an effect of the pipe line mode for the given processing, but has a defect that the performance is significantly reduced for other processings.
- Such reduction in the performance can be compensated to some degree by preparing the operation systems in accordance with the respective processings independently. But the kinds of required arithmetic circuits are increased and the system structure is enlarged, thus resulting in a great increase of the cost.
- each pipe line that is, a period of time necessary for data to be input to the pipe line and then output therefrom, is fixed and the individual pipe lines have different computing times from one another.
- timing control of data transfer between the processors becomes very complicated.
- accor- diong to the conventional processor of the pipe line mode it is difficult to cause processing to be looped within a pipe. Stated differently, processing can not be executed repeatedly within a single pipe line, so that such processing has required intricate software control and a prolonged processing time.
- Such prior microprocessor is operated in the control flow mode where the program counter is employed as an address specifying means to fetch instructions from the memory and the fetched instructions are decoded so as to process data. Consequently, such microprocessor is not suitable for high-speed processing because of the increased number of memory accesses.
- a data flow mode in which data is caused to flow through a bus, a certain arithmetic circuit takes out the data and the result is fed to the next arithmetic circuit through the bus, has the reduced number of memory accesses and hence is fit for high-speed processing.
- This mode has a feature such that predetermined arithmetic processings are carried out on the way of the bus, so that data is transferred while being treated sequentially and the final result is obtained at the end of the bus.
- the data flow mode has a disadvantage such that it is not useful in the art of image processing.
- a data processing machine according to the preamble part of claim 1 is disclosed in "computer design", vol. 19, no. 7, July 1980, pages 97-106, Concord, USA, J. Gurd, et. al.: "Data drive system for high speed parallel computing".
- the output of the processing unit is directly derived from a switch and an input data from the switch is directly sent to a token queue regardless of the output of the processing unit.
- a data processing machine comprising a first memory for storing destination addresses designating locations of instructions, a second memory for storing instructions required to execute a program, a third memory for temporarily storing one data which has reached in advance between two data for an arithmetic operation until another data of said two data will be present, a queue memory for a storing data to be processed and data to be transferred to the outside of said data processing machine, an arithmetic means executing an arithmetic operation according to the instruction read out of said second memory, an interface means transferring a data received from the outside from said data processing machine to said first memory and transferring a data of said queue memory to the outside of said data processing machine and a pipelined bus for coupling said first memory, said second memory, said third memory, said queue memory and said arithmetic means in a ring shape, characterized by further comprising control means coupled to said interface means and said queue memory for controlling data input from said interface means in such a manner that data input from said interface means is inhibited when the number
- the system includes therein a counterfor counting an amount of data stored in a queue memory, a comparator for judging whether or not a value of the counter exceeds an upper limit, that is, a value of (capacity of the queue memory) - (the number of latches constituting the pipe line), and a control circuit adapted to forbid input from the external circuit in accordance with output from the comparator.
- Fig. 1 shows a block diagram of one module.
- This module includes therein a bus interface (BI) 641, a transfer table memory (TT) 642, a parameter table memory (PT) 643, a data memory (DM) 644, a queue memory (QM) 645, a processor unit (PU) 646 and an input data control circuit (IC) 647.
- TT 642, PT 643, DM 644, QM 645 and PU 646 are connected into a ring shape with a pipe line bus in the sequence as illustrated in the drawing.
- Destination address for data is stored in the TT 642.
- the PT 643 is accessed with the destination address output from the TT 642 and stores therein instructions transferred from a host processor in the initialized state.
- the DM 644 serves as a memory for temporarily storing one half of input data for dyadic operation.
- the QM 645 serves as a queue memory allowing to make waiting of data from the DM 644.
- the PU 646 is a processor unit which has a function to perform dyadic operation (i.e., operation for two kinds of input data) or monadic operation (i.e., operation for one kind of input data) with respect to output from the QM 645.
- the BI 641 is an interface circuit for controlling the input/output transfer of data between the pipe line bus and the external bus.
- the PT 643 has such additional functions as to permit generation, extinction and branching of data, counting of incoming data, dyadic control, and address generation for the DM 644.
- the input data control circuit 647 controls the BI 641 upon checking the state of the QM 645.
- Input/output treated in the BI 641 includes module number setting data, template setting data, template reading data, data memory setting data, data memory setting data, data memory reading data, resetting data, ineffective data, passing data, executing data, error status data, and processing data.
- the module number setting data comprises only the module number and is to set the module number into a module number register within the bus interface 641 when reset. After once being set upon resetting, the content of the module number register remains unchanged until a reset signal will become newly active. The content of the module number register is used to be compared with the module number of data taken into the processing module after resetting.
- the template setting data comprises the module number, address for the transfer table memory 642, a data value written into the transfer table memory 642, address for the parameter table memory 643 and a data value written into the parameter table memory 643.
- the template setting data is to set template data into the transfer table memory 642 and the parameter table memory 643.
- the template data represents the content and procedure of processing and is normally transferred into the internal processing module, that is, into the transfer table memory 642 and the parameter table memory 643, from a host processor on the outside at the starting of serial processing.
- the template reading data comprises the module number, address for the transfer table memory 642 and address for the parameter table memory 643.
- the template reading data is to read the template data set in the transfer table memory 642 and the parameter table memory 643.
- the module number for the data there there is used the number of module which is intended to read the template data therefrom.
- the template reading data can be utilized to check the content of the template data in the event there occurs an error.
- the template reading data serves to output the read- out data value to the external circuit, but the module number at this time is replaced of the specified module number (e.g., 1) in order to discriminate it from other data.
- the data memory setting data comprises the module number and a data value, and is to write the data value into the data memory 644. Addresses used for writing the data value into the data memory 644 are generated from the parameter table memory 643 while being sequentially incremented one by one from 0.
- the data memory reading data comprises the module number and address for the data memory 644. The data memory reading data is to access the data memory 644 with the address for the data memory 644 included therein and to output the read-out data value to the external circuit.
- the resetting data comprises only the module number and is used to release the error state after there has occurred such state within the processing module.
- the error state is resulted from an overflow error in the queue memory 645. If this error occurs, the data input to the bus interface 641 is not taken into the processing module and is extinguished. But in the case the resetting data is input to the bus interface 641, the error state is released and normal processing will be continued after that.
- the resetting data has another function to initialize the state within the processing module, that is, to clear counters and memories included therein. The resetting data disappears within the bus interface 641.
- the ineffective data comprises only the specified module number (e.g., 0). This data will disappear within the bus interface 641, even if it should be input to the processing module.
- the passage data represents such data as having therein the module number which does not coincide with the content of the module number register set at the time of resetting, and as not constituting the ineffective data as well as the module number setting data.
- the passing data input from the external data directly passes through the bus interface 641 and is then output to the external circuit. This means the bypassing of data.
- the executing data comprises the module number, address for the transfer table memory 642, a control bit, a code bit and a data value.
- the control bit is set when the result of operation in the processor unit 646 coincides with the designated condition.
- address in the transfer table memory 642 is changed upon the designation of a branching instruction by the processor unit 646. Stated differently, in such case the data will be processed in a manner different from the data where the control bit is not set. With the branching instruction not being designated, no change of processing will occur so that the control bit and the branching instruction are normally used as a pair.
- the branching instruction is used to change a flow of processing in accordance with the operation result.
- the error status data comprises the module number and error status.
- the error status data has a function to inform the external circuit of the occurrence of error, when there occurs an overflow error in the queue memory 645 within the processing module.
- the module number included in the error status data corresponds to the readout content of the module number register set within the module which has been subject to the error.
- the processing data comprises the module number, address for the transfer table memory 642, a control bit, a code bit and a data value.
- the processing data makes reference to the transfer table memory 642 and the parameter table memory 643.
- the processing data is added with address for the transfer table memory 642 and the module number obtained by referring to the transfer table memory 642 and the parameter table memory 643, and then output to the external circuit.
- the executing data comprises the module number, address for the transfer table memory 642, a control bit, a code bit and a data value.
- This data is taken into the ring-shaped bus of pipe line mode from the external circuit via the bus interface 641 and then sent to the transfer table memory 642.
- the data is allowed to be input from the external circuit into the processing module only on such conditions that the processor unit 6 is not under output operation, the number of data stored in the queue memory 645 is less than a certain value (e.g., 16 data), and the module number included in the input data coincides with the content of the module number register which has been taken therein at the time of resetting.
- the data input from the external circuit to the bus interface 641 is added with a use bit within bus interface 641 and then sent to the transfer table memory 642.
- the transfer table memory 642 receives data from the bus interface 641 or the processor unit 646.
- the data input to the transfer table memory 642 comprises a data value, address for the transfer table memory 642, use flag and a template flag.
- the use flag is to indicate whether the data is effective or ineffective.
- the transfer table memory 642 checks both use flags of output data from the processor unit 646 and the bus interface 641, and then takes therein the data with its use flag assuming "1". In the case both use flags assume "1", the output data from the processor unit 646 is taken in with priority. The data in such a case where both use flags assume "0", will turn to ineffective data. This ineffective data passes through the transfer table memory 642, parameter table memory 643 and the data memory 644, and then it disappears before reaching the queue memory 645.
- the transfer table memory 642 judges the input data as normal processing data, so that the transfer table memory 642 is accessed with the address for the transfer table memory 642 and then the read-out data is sent to the parameter table memory 643. With the use flag assuming "1" and the template flag assuming "1”, the data is written into and read out from the transfer table memory 642 with the control bit.
- the data written into the transfer table memory 642 comprises information to discriminate processings before and after the reference to the transfer table memory 642, and information to discriminate paired components from each other when addresses used for newly referring to the transfer table memory 642, addresses used for referring to the parameter table memory 643 and the data sent to the parameter table memory 643 are operated as a pair, respectively, after data processing in the processor unit 646.
- the parameter table memory 643 is referred with the address for the parameter table memory 643, which is included in the data read out from the transfer table memory 642.
- the parameter table memory 643 mainly stores therein codes of instructions. Such codes include information to control data exchange where two data are operated as a pair, code information to designate the number of output data, the module number attached to the data taken out to the external circuit and the content of processing in the processor unit 646, and information for supervising the states such as reading/writing of the data memory 644, dyadic queue control of data or flow rate control thereof.
- Writing of data into the parameter table memory 643 is effected when the template flag is set. This data is divided into permanent information which content remains unchanged during normal processing and temporary information which constitutes address information for the data memory 644.
- the parameter table memory 643 receives the use flag, template flag, control bit, instruction code and a data exchange signal from the transfer table memory 642, and it outputs a write enable signal to the data memory 644.
- the data memory 644 is used for storing a queue in which the data having reached in advance is allowed to temporarily wait until both data for dyadic operation (i.e., operating using two kinds of data as input) will be all present, a constant used for constant operation, a look up table, a transition table for processing the transition of state, and input/output data.
- the write enable signal for the data memory 644 is sent from the parameter table memory 643. With the instruction of dyadic operation being designated and both data being all present, input data from the parameter table memory 643 and read data from the data memory 644 are output to the queue memory 645 at the same time.
- the queue memory 645 comprises a data queue and a generator queue.
- the data queue serves as a memory for temporarily holding data in the case the processor unit 646 outputs the plural number of data or receives data from the bus interface 641, because the processor unit 646 becomes busy and unable to input any more data at that time.
- the generator queue receives starting data for generating a numerical value, the number of generated data and control information from the data memory, and it outputs data to the processor unit 646 upon checking the information indicative of whether or not the data queue has a vacant space more than a predetermined value (a half of capacity of the data queue in this embodiment.
- the processor unit 646 comprises arithmetic circuits which have various functions to permit arithmetic operation, logical operation, shift, comparison, bit inversion, priority encoding, branching, generation of numeric value, and copying.
- the bit inversion means such processing as providing an output data value which has an inverted bit position with respect to an input data value.
- a value of each bit included in the input data value is sequentially checked from a bit with highest priority to a bit with lowest priority. As a result of this check, when there appears a bit which assumes "1" for the first, a position of the bit is indicated in the form of binary integer and this is turned into the output data value.
- the branching performs such processing that upon checking the control bit, the address for the template memory 642 included in the input data is directly output as the address for the template memory 642 included in the output data with the control bit assuming "0", while address obtained by incrementing the address for the template memory 642 included in the input data is output as the address for the template memory 642 included in the output data with the control bit assuming "1".
- the generation of numeric value performs such processing as which checks a data value in the input data, the number of generations and an increment value, then adds the increment value to the data value in the input data corresponding to the number of generations, and then issues the output data corresponding to the number of generations.
- This function is used in the case of including repetitive processing or including a need to generate addresses for the memory. On this occasion, the address for the transfer table memory 642 in the output data remains unchanged and the address for the transfer table memory 642 in the input data is directly output.
- the copying performs such processing that a data value in the input data and the number of copyings are checked and the data value in the input data is directly copied into the output data corresponding to the number of copyings.
- the address for the transfer table memory 642 included in the output data assumes a value which is obtained by incrementing the address for the transfer table memory 642 in the input data one by one in sequence of outputs.
- the number of input data to the processor unit 646 is one or two, while the number of output data can be designated to have a range of 1 to 16. Processing where the number of input data is one is called as monadic operation, and processing where the number of input data is two is called as dyadic operation. In the case of monadic operation, it is not required to make waiting because the number of input data is one, while in the case of dyadic operation, the data having reached in advance is stored in a dyadic queue within the data memory 644 to make waiting because it is impossible to execute processing until both data will be completely present.
- the delayed data when it has reached, it is sent to the processor unit 646 through the queue memory 645 together with the former data read out from the dyadic queue within the data memory. Whereupon, the operation will be started. In other words, the dyadic operation will be subject to execution control in a data flow mode.
- a busy flag is set while being output so as to inhibit the data to be input from the queue memory 645.
- Fig. 2 shows a block diagram showing one embodiment of the input data control circuit 647 shown in Fig. 1.
- This newly proposed circuit 647 includes therein a counter 751, a comparator 752 and a register 753.
- the reference numeral 761 denotes data written into the register 753, and 762 denotes a write pulse fed to the register 753.
- An upper limit setting value for preventing an overflow in the queue memory 645 shown in Fig. 1 is preset into the register 753 by the write pulse 762. Through the subsequent processing, the preset value remains unchanged.
- the reference numeral 763 denotes a reset signal, which is to clear the counter 751 prior to processing.
- the numeral 764 denotes a clock signal for the counter 751.
- a value of the counter751 is incremented by one when the clock signal 764 is input to the counter 751.
- a value of the counter 751 is decremented by one when the clock signal 764 is input to the counter 751.
- the value of the counter 751 indicates the number of data stored in the queue memory 645 shown in Fig. 1 at present.
- the reference numeral 766 denotes data read-out from the counter 751 and sent to the comparator 752 and the queue memory 645 in Fig.
- the numeral 767 denotes data read-out from the register 753, that is, the upper limit setting value as mentioned above.
- the comparator 752 makes comparison between the output data 766 from the counter 751 and the output data 767 from the register 753. As a result of the comparison, if the output data 766 from the counter 751 is larger, there issues a data input inhibition signal 768 which is output to the bus interface 641 shown in 1.
- This data input inhibition signal 768 is used as an input control signal in the bus interface 641, so that data input is forbidden while the data input inhibition signal 768 is active, that is, while the number of data stored in the queue memory 645 exceeds the aforesaid upper limit. As the data input inhibition signal 768 becomes inactive, data input will be started once again.
- the reason why a difference between capacity of the queue memory 645 and the number of latches constituting the pipe line is adopted as the upper limit value is as follows.
- the data in the queue memory 645 includes data to be output to the external circuit through the bus interface 641. At this time, if the bus in the external circuit is in the busy state, the data is unable to be output. But even such occasion, the latches constituting the pipe line continue operation thereof, so that data in amount corresponding to the number of latches is caused to flow into the queue memory 645 even with data input from the external circuit being inhibited, thus producing a possibility of overflow. Therefore, the upper limit value is determined to avoid such possibility.
- the data processing system is characterized in that for the purpose of preventing an overflow in the queue memory allowing data to wait for another, there is included the input data control circuit which monitors an amount of data stored in the queue memory and which inhibits input of data temporarily to avoid occurrence of the overflow.
- This control is performed so as to forbid input of data when the sum of the maximum amount of data generated at one time and the amount of data stored in the queue memory exceeds capacity of the queue memory.
- the number of data stored in the queue memory becomes less than the value of (capacity of the queue memory) - (data amount generated at one time)
- data input is released from is inhibited state and then started once again.
- the data processing machine of modular type as shown in Figs. 1 and 2 is programmable and easy in busy connection, so that it is also fit for a composite processing system.
- transfer of instructions to each module that is, setting of the initial state
- a general microcomputer is able to be used as a host processor.
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Description
- The present invention relates to a data processing machine according to the preamble of claim 1.
- There has been heretofore adopted a control flow mode in microprocessors as well known. A basic process of this mode is such that a necessary instruction is fetched by accessing to a memory, the fetched instruction is decoded to read out data and execute the processing specified by the instruction, and the result is stored in the memory. Such process is sequentially repeated so as to proceess a set of program. In order to apply the processor of this kind to the art (e.g., image processing or voice processing) which requires high-speed processing, there has been developed in the past such an attempt as improving an operating speed of semiconductor devices used for the processor or increasing the number of bits treated in the processor at the same time. In the present situation, however, the former is limited due to difficulties in the semiconductor manufacturing technology and the latter leads to an increase in size of the device and system and has a limit from the view point of economy.
- Under the background as mentioned above, a pipe line mode has been proposed as an architecture adaptable to a high-speed processing required. This mode is based on parallel processing of data and is to control the respective operation flows (i.g., addition processing, subtraction processing, multiplication processiong or division processing) for processing of programs in parallel. A processor system employing the pipe line mode is so structured that a plurality of arithmetic circuits each having a fixed single function, such as an adder or multiplier, are connected to each other in a ring form with a bus of the pipe line mode. This system is suitable for high-speed processing in that a plurality of operation flows can be executed in parallel. It is required, however, to select the kind of arithmetic circuits to be used and determine the sequencde of the selected arithmetic circuits optimum for the given processing. Therefore, the operation system thus structured can produce an effect of the pipe line mode for the given processing, but has a defect that the performance is significantly reduced for other processings. Such reduction in the performance can be compensated to some degree by preparing the operation systems in accordance with the respective processings independently. But the kinds of required arithmetic circuits are increased and the system structure is enlarged, thus resulting in a great increase of the cost. Furthermore, the computing time in each pipe line, that is, a period of time necessary for data to be input to the pipe line and then output therefrom, is fixed and the individual pipe lines have different computing times from one another. As a result, in the case a plurality of processors of the pipe line mode are used to constitute the so-called multiprocessor, timing control of data transfer between the processors becomes very complicated. In addition, accor- diong to the conventional processor of the pipe line mode, it is difficult to cause processing to be looped within a pipe. Stated differently, processing can not be executed repeatedly within a single pipe line, so that such processing has required intricate software control and a prolonged processing time.
- Meanwhile, in the art requiring high-speed processing (e.g., image processing adapted to process images from satellites or of X-ray photographs by a man-machine system), a large amount of data up to about 6 millions pixels for each image has to be processed in a short period of time. For instance, to process one image for 3 seconds, the image has to be processed at a speed of 500 ns per 1 pixel. It is required, therefore, that the processor itself has a function to permit high-speed processing and that data transfer between the processor and the memory can be performed at a high speed. Particularly, the latter is a major problem for the conventional microprocessor in which the memory is accessed by using a program counter. As mentioned above, such prior microprocessor is operated in the control flow mode where the program counter is employed as an address specifying means to fetch instructions from the memory and the fetched instructions are decoded so as to process data. Consequently, such microprocessor is not suitable for high-speed processing because of the increased number of memory accesses.
- To the contrary, a data flow mode in which data is caused to flow through a bus, a certain arithmetic circuit takes out the data and the result is fed to the next arithmetic circuit through the bus, has the reduced number of memory accesses and hence is fit for high-speed processing. This mode has a feature such that predetermined arithmetic processings are carried out on the way of the bus, so that data is transferred while being treated sequentially and the final result is obtained at the end of the bus. In the data flow mode, however, it is difficult to control the flow of data and make coupling with the prior microprocessor. Therefore, an effect meeting expectations can not be obtained in repetitive operations, parallel processing or composite processing using a common bus. In other words, the data flow mode has a disadvantage such that it is not useful in the art of image processing.
- A data processing machine according to the preamble part of claim 1 is disclosed in "computer design", vol. 19, no. 7, July 1980, pages 97-106, Concord, USA, J. Gurd, et. al.: "Data drive system for high speed parallel computing". In this device the output of the processing unit is directly derived from a switch and an input data from the switch is directly sent to a token queue regardless of the output of the processing unit.
- Therefore, when a new data is sent to the token queue in the case when it is full of start data, the start data are destroyed. On the other hand, to avoid this destruction, the storing operation of the token queue is performed at a low speed in comparison with the processing speed of the processor unit. However, the processing speed of the processing unit depends on the program to be executed, and therefore the control of a switch becomes very complex.
- It is the object of the present invention to provide a data processing machine which has a function of controlling the flow rate of data and is able to prevent an internal memory from falling into an overflow state.
- This object is achieved by a data processing machine comprising a first memory for storing destination addresses designating locations of instructions, a second memory for storing instructions required to execute a program, a third memory for temporarily storing one data which has reached in advance between two data for an arithmetic operation until another data of said two data will be present, a queue memory for a storing data to be processed and data to be transferred to the outside of said data processing machine, an arithmetic means executing an arithmetic operation according to the instruction read out of said second memory, an interface means transferring a data received from the outside from said data processing machine to said first memory and transferring a data of said queue memory to the outside of said data processing machine and a pipelined bus for coupling said first memory, said second memory, said third memory, said queue memory and said arithmetic means in a ring shape, characterized by further comprising control means coupled to said interface means and said queue memory for controlling data input from said interface means in such a manner that data input from said interface means is inhibited when the number of data stored in said queue memory has reached a limit value corresponding to the difference between the capacity of the queue memory and the number of latches constituting the pipelined bus.
- The above object and other features and advantages of the present invention will become apparent from the following description of preferred embodiments thereof taken in conjunction with the accompanying drawings:
- Fig. 1 is a block diagram of a data processing machine according to an embodiment of the invention;
- Fig. 2 is a block diagram showing one embodiment of an input data control circuit in Fig. 1;
- Hereinafter one embodiment of the processor system will be described by referring to Fig. 1.
- The system according to this embodiment includes therein a counterfor counting an amount of data stored in a queue memory, a comparator for judging whether or not a value of the counter exceeds an upper limit, that is, a value of (capacity of the queue memory) - (the number of latches constituting the pipe line), and a control circuit adapted to forbid input from the external circuit in accordance with output from the comparator.
- Fig. 1 shows a block diagram of one module. This module includes therein a bus interface (BI) 641, a transfer table memory (TT) 642, a parameter table memory (PT) 643, a data memory (DM) 644, a queue memory (QM) 645, a processor unit (PU) 646 and an input data control circuit (IC) 647. These members TT 642, PT 643, DM 644, QM 645 and PU 646 are connected into a ring shape with a pipe line bus in the sequence as illustrated in the drawing. Destination address for data is stored in the
TT 642. The PT 643 is accessed with the destination address output from the TT 642 and stores therein instructions transferred from a host processor in the initialized state. TheDM 644 serves as a memory for temporarily storing one half of input data for dyadic operation. TheQM 645 serves as a queue memory allowing to make waiting of data from theDM 644. ThePU 646 is a processor unit which has a function to perform dyadic operation (i.e., operation for two kinds of input data) or monadic operation (i.e., operation for one kind of input data) with respect to output from theQM 645. TheBI 641 is an interface circuit for controlling the input/output transfer of data between the pipe line bus and the external bus. ThePT 643 has such additional functions as to permit generation, extinction and branching of data, counting of incoming data, dyadic control, and address generation for theDM 644. The inputdata control circuit 647 controls theBI 641 upon checking the state of theQM 645. - Input/output treated in the
BI 641 includes module number setting data, template setting data, template reading data, data memory setting data, data memory setting data, data memory reading data, resetting data, ineffective data, passing data, executing data, error status data, and processing data. - The module number setting data comprises only the module number and is to set the module number into a module number register within the
bus interface 641 when reset. After once being set upon resetting, the content of the module number register remains unchanged until a reset signal will become newly active. The content of the module number register is used to be compared with the module number of data taken into the processing module after resetting. The template setting data comprises the module number, address for thetransfer table memory 642, a data value written into thetransfer table memory 642, address for theparameter table memory 643 and a data value written into theparameter table memory 643. The template setting data is to set template data into thetransfer table memory 642 and theparameter table memory 643. The template data represents the content and procedure of processing and is normally transferred into the internal processing module, that is, into thetransfer table memory 642 and theparameter table memory 643, from a host processor on the outside at the starting of serial processing. The template reading data comprises the module number, address for thetransfer table memory 642 and address for theparameter table memory 643. The template reading data is to read the template data set in thetransfer table memory 642 and theparameter table memory 643. As the module number for the data there is used the number of module which is intended to read the template data therefrom. Moreover, the template reading data can be utilized to check the content of the template data in the event there occurs an error. After reading out the template data, the template reading data serves to output the read- out data value to the external circuit, but the module number at this time is replaced of the specified module number (e.g., 1) in order to discriminate it from other data. - The data memory setting data comprises the module number and a data value, and is to write the data value into the
data memory 644. Addresses used for writing the data value into thedata memory 644 are generated from theparameter table memory 643 while being sequentially incremented one by one from 0. The data memory reading data comprises the module number and address for thedata memory 644. The data memory reading data is to access thedata memory 644 with the address for thedata memory 644 included therein and to output the read-out data value to the external circuit. - The resetting data comprises only the module number and is used to release the error state after there has occurred such state within the processing module. The error state is resulted from an overflow error in the
queue memory 645. If this error occurs, the data input to thebus interface 641 is not taken into the processing module and is extinguished. But in the case the resetting data is input to thebus interface 641, the error state is released and normal processing will be continued after that. Other than the above function to reset the error state, the resetting data has another function to initialize the state within the processing module, that is, to clear counters and memories included therein. The resetting data disappears within thebus interface 641. - The ineffective data comprises only the specified module number (e.g., 0). This data will disappear within the
bus interface 641, even if it should be input to the processing module. - The passage data represents such data as having therein the module number which does not coincide with the content of the module number register set at the time of resetting, and as not constituting the ineffective data as well as the module number setting data. The passing data input from the external data directly passes through the
bus interface 641 and is then output to the external circuit. This means the bypassing of data. - The executing data comprises the module number, address for the
transfer table memory 642, a control bit, a code bit and a data value. The control bit is set when the result of operation in theprocessor unit 646 coincides with the designated condition. In the case the control bit is set, address in thetransfer table memory 642 is changed upon the designation of a branching instruction by theprocessor unit 646. Stated differently, in such case the data will be processed in a manner different from the data where the control bit is not set. With the branching instruction not being designated, no change of processing will occur so that the control bit and the branching instruction are normally used as a pair. The branching instruction is used to change a flow of processing in accordance with the operation result. The error status data comprises the module number and error status. The error status data has a function to inform the external circuit of the occurrence of error, when there occurs an overflow error in thequeue memory 645 within the processing module. The module number included in the error status data corresponds to the readout content of the module number register set within the module which has been subject to the error. - The processing data comprises the module number, address for the
transfer table memory 642, a control bit, a code bit and a data value. The processing data makes reference to thetransfer table memory 642 and theparameter table memory 643. As a result, upon the presence of an output instruction, the processing data is added with address for thetransfer table memory 642 and the module number obtained by referring to thetransfer table memory 642 and theparameter table memory 643, and then output to the external circuit. - Hereinafter there will be described in detail a flow of data in the operation processing.
- The executing data comprises the module number, address for the
transfer table memory 642, a control bit, a code bit and a data value. This data is taken into the ring-shaped bus of pipe line mode from the external circuit via thebus interface 641 and then sent to thetransfer table memory 642. The data is allowed to be input from the external circuit into the processing module only on such conditions that the processor unit 6 is not under output operation, the number of data stored in thequeue memory 645 is less than a certain value (e.g., 16 data), and the module number included in the input data coincides with the content of the module number register which has been taken therein at the time of resetting. - The data input from the external circuit to the
bus interface 641 is added with a use bit withinbus interface 641 and then sent to thetransfer table memory 642. - The
transfer table memory 642 receives data from thebus interface 641 or theprocessor unit 646. The data input to thetransfer table memory 642 comprises a data value, address for thetransfer table memory 642, use flag and a template flag. The use flag is to indicate whether the data is effective or ineffective. Thetransfer table memory 642 checks both use flags of output data from theprocessor unit 646 and thebus interface 641, and then takes therein the data with its use flag assuming "1". In the case both use flags assume "1", the output data from theprocessor unit 646 is taken in with priority. The data in such a case where both use flags assume "0", will turn to ineffective data. This ineffective data passes through thetransfer table memory 642,parameter table memory 643 and thedata memory 644, and then it disappears before reaching thequeue memory 645. - With the use flag assuming "1" and the template flag assuming "0", the
transfer table memory 642 judges the input data as normal processing data, so that thetransfer table memory 642 is accessed with the address for thetransfer table memory 642 and then the read-out data is sent to theparameter table memory 643. With the use flag assuming "1" and the template flag assuming "1", the data is written into and read out from thetransfer table memory 642 with the control bit. - The data written into the
transfer table memory 642 comprises information to discriminate processings before and after the reference to thetransfer table memory 642, and information to discriminate paired components from each other when addresses used for newly referring to thetransfer table memory 642, addresses used for referring to theparameter table memory 643 and the data sent to theparameter table memory 643 are operated as a pair, respectively, after data processing in theprocessor unit 646. - The
parameter table memory 643 is referred with the address for theparameter table memory 643, which is included in the data read out from thetransfer table memory 642. Theparameter table memory 643 mainly stores therein codes of instructions. Such codes include information to control data exchange where two data are operated as a pair, code information to designate the number of output data, the module number attached to the data taken out to the external circuit and the content of processing in theprocessor unit 646, and information for supervising the states such as reading/writing of thedata memory 644, dyadic queue control of data or flow rate control thereof. Writing of data into theparameter table memory 643 is effected when the template flag is set. This data is divided into permanent information which content remains unchanged during normal processing and temporary information which constitutes address information for thedata memory 644. - The
parameter table memory 643 receives the use flag, template flag, control bit, instruction code and a data exchange signal from thetransfer table memory 642, and it outputs a write enable signal to thedata memory 644. - The
data memory 644 is used for storing a queue in which the data having reached in advance is allowed to temporarily wait until both data for dyadic operation (i.e., operating using two kinds of data as input) will be all present, a constant used for constant operation, a look up table, a transition table for processing the transition of state, and input/output data. The write enable signal for thedata memory 644 is sent from theparameter table memory 643. With the instruction of dyadic operation being designated and both data being all present, input data from theparameter table memory 643 and read data from thedata memory 644 are output to thequeue memory 645 at the same time. Thequeue memory 645 comprises a data queue and a generator queue. The data queue serves as a memory for temporarily holding data in the case theprocessor unit 646 outputs the plural number of data or receives data from thebus interface 641, because theprocessor unit 646 becomes busy and unable to input any more data at that time. - The generator queue receives starting data for generating a numerical value, the number of generated data and control information from the data memory, and it outputs data to the
processor unit 646 upon checking the information indicative of whether or not the data queue has a vacant space more than a predetermined value (a half of capacity of the data queue in this embodiment. - The
processor unit 646 comprises arithmetic circuits which have various functions to permit arithmetic operation, logical operation, shift, comparison, bit inversion, priority encoding, branching, generation of numeric value, and copying. - The bit inversion means such processing as providing an output data value which has an inverted bit position with respect to an input data value.
- In processing referred as the priority encoding, a value of each bit included in the input data value is sequentially checked from a bit with highest priority to a bit with lowest priority. As a result of this check, when there appears a bit which assumes "1" for the first, a position of the bit is indicated in the form of binary integer and this is turned into the output data value.
- The branching performs such processing that upon checking the control bit, the address for the
template memory 642 included in the input data is directly output as the address for thetemplate memory 642 included in the output data with the control bit assuming "0", while address obtained by incrementing the address for thetemplate memory 642 included in the input data is output as the address for thetemplate memory 642 included in the output data with the control bit assuming "1". - The generation of numeric value performs such processing as which checks a data value in the input data, the number of generations and an increment value, then adds the increment value to the data value in the input data corresponding to the number of generations, and then issues the output data corresponding to the number of generations. This function is used in the case of including repetitive processing or including a need to generate addresses for the memory. On this occasion, the address for the
transfer table memory 642 in the output data remains unchanged and the address for thetransfer table memory 642 in the input data is directly output. - The copying performs such processing that a data value in the input data and the number of copyings are checked and the data value in the input data is directly copied into the output data corresponding to the number of copyings. At this time, the address for the
transfer table memory 642 included in the output data assumes a value which is obtained by incrementing the address for thetransfer table memory 642 in the input data one by one in sequence of outputs. - The number of input data to the
processor unit 646 is one or two, while the number of output data can be designated to have a range of 1 to 16. Processing where the number of input data is one is called as monadic operation, and processing where the number of input data is two is called as dyadic operation. In the case of monadic operation, it is not required to make waiting because the number of input data is one, while in the case of dyadic operation, the data having reached in advance is stored in a dyadic queue within thedata memory 644 to make waiting because it is impossible to execute processing until both data will be completely present. More specifically, when the delayed data has reached, it is sent to theprocessor unit 646 through thequeue memory 645 together with the former data read out from the dyadic queue within the data memory. Whereupon, the operation will be started. In other words, the dyadic operation will be subject to execution control in a data flow mode. - When the number of output data is two or more, a busy flag is set while being output so as to inhibit the data to be input from the
queue memory 645. - Fig. 2 shows a block diagram showing one embodiment of the input
data control circuit 647 shown in Fig. 1. - This newly proposed
circuit 647 includes therein acounter 751, acomparator 752 and aregister 753. Thereference numeral 761 denotes data written into theregister register 753. An upper limit setting value for preventing an overflow in thequeue memory 645 shown in Fig. 1 is preset into theregister 753 by thewrite pulse 762. Through the subsequent processing, the preset value remains unchanged. Thereference numeral 763 denotes a reset signal, which is to clear thecounter 751 prior to processing. The numeral 764 denotes a clock signal for thecounter 751. With an up/down switching signal 765 assuming the upstate, a value of the counter751 is incremented by one when the clock signal 764 is input to thecounter 751. Meanwhile, with the up/down switching signal 765 assuming the down-state, a value of thecounter 751 is decremented by one when the clock signal 764 is input to thecounter 751. The value of thecounter 751 indicates the number of data stored in thequeue memory 645 shown in Fig. 1 at present. Thus, upon write into thequeue memory 645, the value is incremented by one, while upon read-out from thequeue memory 645, the value is decremented by one. Thereference numeral 766 denotes data read-out from thecounter 751 and sent to thecomparator 752 and thequeue memory 645 in Fig. 1. The numeral 767 denotes data read-out from theregister 753, that is, the upper limit setting value as mentioned above. Thecomparator 752 makes comparison between theoutput data 766 from thecounter 751 and theoutput data 767 from theregister 753. As a result of the comparison, if theoutput data 766 from thecounter 751 is larger, there issues a datainput inhibition signal 768 which is output to thebus interface 641 shown in 1. This datainput inhibition signal 768 is used as an input control signal in thebus interface 641, so that data input is forbidden while the datainput inhibition signal 768 is active, that is, while the number of data stored in thequeue memory 645 exceeds the aforesaid upper limit. As the datainput inhibition signal 768 becomes inactive, data input will be started once again. - The reason why a difference between capacity of the
queue memory 645 and the number of latches constituting the pipe line is adopted as the upper limit value is as follows. The data in thequeue memory 645 includes data to be output to the external circuit through thebus interface 641. At this time, if the bus in the external circuit is in the busy state, the data is unable to be output. But even such occasion, the latches constituting the pipe line continue operation thereof, so that data in amount corresponding to the number of latches is caused to flow into thequeue memory 645 even with data input from the external circuit being inhibited, thus producing a possibility of overflow. Therefore, the upper limit value is determined to avoid such possibility. - According to the forgoing control, it becomes possible to prevent the
queue memory 645 from falling into the overflow state. Further, in the case of multistage connection, data is able to flow at a speed fit for the processor module having the lowest processing speed without a need of taking special consideration on the allocation of processings. - As described hereinabove, the data processing system according to this embodiment is characterized in that for the purpose of preventing an overflow in the queue memory allowing data to wait for another, there is included the input data control circuit which monitors an amount of data stored in the queue memory and which inhibits input of data temporarily to avoid occurrence of the overflow. This control is performed so as to forbid input of data when the sum of the maximum amount of data generated at one time and the amount of data stored in the queue memory exceeds capacity of the queue memory. As the number of data stored in the queue memory becomes less than the value of (capacity of the queue memory) - (data amount generated at one time), data input is released from is inhibited state and then started once again. As a result, there can be eliminated such a need as reforming the program due to occurrence of an overflow error, thus resulting in that programs can be desirously arranged taking no consideration on a possibility of overflow.
- The data processing machine of modular type as shown in Figs. 1 and 2 is programmable and easy in busy connection, so that it is also fit for a composite processing system. In addition, since transfer of instructions to each module (that is, setting of the initial state) can be performed with ease, a general microcomputer is able to be used as a host processor.
Claims (1)
- A data processing machine comprising a first memory (642) for storing destinaton addresses designating locations of instructions, a second memory (643) for storing instructions required to execute a program, a third memory (644) for temporarily storing one data which has reached in advance between two data for an arithmetic operation until another data of said two data will be present, a queue memory (645) for storing data to be processed and data to be transferred to the outside of said data processing machine, an arithmetic means (646) executing an arithmetic operation according to the instruction read out of said second memory (643), an interface means (641) transferring a data received from the outside of said data processing machine to said first memory and transferring a data of said queue memory (645) to the outside of said data processing machine, and a pipelined bus for coupling said first memory, said second memory, said third memory, said queue memory and said arithmetic means in a ring shape, characterized by further comprising control means (647) coupled to said interface means (641) and said queue memory (645) for controlling data input from said interface means (641) in such manner that data input from said interface means (641) is inhibited when the number of data stored in said queue memory (645) has reached a limit value corresponding to the difference between the capacity of the queue memory and the number of latches constituting the pipelined bus.
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56169152A JPS5870360A (en) | 1981-10-22 | 1981-10-22 | Data flow processor |
JP169152/81 | 1981-10-22 | ||
JP201272/81 | 1981-12-14 | ||
JP56201272A JPS58103037A (en) | 1981-12-14 | 1981-12-14 | Queue memory device |
JP57002985A JPS58121453A (en) | 1982-01-12 | 1982-01-12 | Processor module |
JP2985/82 | 1982-01-12 | ||
JP10309/82 | 1982-01-26 | ||
JP57010309A JPS58127249A (en) | 1982-01-26 | 1982-01-26 | Controlling of data flow rate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP82109783.9 Division | 1982-10-22 |
Publications (3)
Publication Number | Publication Date |
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EP0172522A2 EP0172522A2 (en) | 1986-02-26 |
EP0172522A3 EP0172522A3 (en) | 1987-05-06 |
EP0172522B1 true EP0172522B1 (en) | 1991-01-02 |
Family
ID=27453757
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP82109783A Expired EP0078034B1 (en) | 1981-10-22 | 1982-10-22 | Data processing machine suitable for high-speed processing |
EP85110111A Expired - Lifetime EP0176712B1 (en) | 1981-10-22 | 1982-10-22 | Data-processing system comprising a host processor and data-driven modules |
EP85110112A Expired - Lifetime EP0172522B1 (en) | 1981-10-22 | 1982-10-22 | Data processing machine suitable for high-speed processing |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
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EP82109783A Expired EP0078034B1 (en) | 1981-10-22 | 1982-10-22 | Data processing machine suitable for high-speed processing |
EP85110111A Expired - Lifetime EP0176712B1 (en) | 1981-10-22 | 1982-10-22 | Data-processing system comprising a host processor and data-driven modules |
Country Status (3)
Country | Link |
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US (2) | US4594653A (en) |
EP (3) | EP0078034B1 (en) |
DE (3) | DE3275139D1 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60101644A (en) * | 1983-11-07 | 1985-06-05 | Masahiro Sowa | Parallel processing computer |
US4821174A (en) * | 1984-03-20 | 1989-04-11 | Westinghouse Electric Corp. | Signal processing system including a bus control module |
JPS61276032A (en) * | 1985-05-31 | 1986-12-06 | Matsushita Electric Ind Co Ltd | Information processing device |
JPS63129425A (en) * | 1986-11-19 | 1988-06-01 | Mitsubishi Electric Corp | Data processor |
US4942520A (en) * | 1987-07-31 | 1990-07-17 | Prime Computer, Inc. | Method and apparatus for indexing, accessing and updating a memory |
US4845663A (en) * | 1987-09-03 | 1989-07-04 | Minnesota Mining And Manufacturing Company | Image processor with free flow pipeline bus |
JPH03500461A (en) * | 1988-07-22 | 1991-01-31 | アメリカ合衆国 | Data flow device for data-driven calculations |
US5291615A (en) * | 1988-08-11 | 1994-03-01 | Kabushiki Kaisha Toshiba | Instruction pipeline microprocessor |
JP2564624B2 (en) * | 1988-09-20 | 1996-12-18 | 富士通株式会社 | Stack method |
US5117486A (en) * | 1989-04-21 | 1992-05-26 | International Business Machines Corp. | Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor |
US5517626A (en) * | 1990-05-07 | 1996-05-14 | S3, Incorporated | Open high speed bus for microcomputer system |
EP0528399A3 (en) * | 1991-08-19 | 1994-12-21 | Toyoda Machine Works Ltd | Method and apparatus for learning of neural network |
US5367638A (en) * | 1991-12-23 | 1994-11-22 | U.S. Philips Corporation | Digital data processing circuit with control of data flow by control of the supply voltage |
US5842033A (en) * | 1992-06-30 | 1998-11-24 | Discovision Associates | Padding apparatus for passing an arbitrary number of bits through a buffer in a pipeline system |
DE69327504T2 (en) * | 1992-10-19 | 2000-08-10 | Koninkl Philips Electronics Nv | Data processor with operational units that share groups of register memories |
US5764995A (en) * | 1994-03-25 | 1998-06-09 | Packard Bell Nec | Write once read only registers |
US5590304A (en) * | 1994-06-13 | 1996-12-31 | Covex Computer Corporation | Circuits, systems and methods for preventing queue overflow in data processing systems |
KR100357338B1 (en) * | 1994-08-02 | 2003-02-11 | 가부시끼가이샤 히다치 세이사꾸쇼 | Data processing system |
RU2130198C1 (en) * | 1997-08-06 | 1999-05-10 | Бурцев Всеволод Сергеевич | Computer |
FR2771526B1 (en) * | 1997-11-27 | 2004-07-23 | Bull Sa | ARCHITECTURE FOR MANAGING VITAL DATA IN A MULTI-MODULAR MACHINE AND METHOD FOR IMPLEMENTING SUCH AN ARCHITECTURE |
JP3983455B2 (en) * | 2000-04-13 | 2007-09-26 | シャープ株式会社 | Execution control apparatus for data driven information processing apparatus |
AU767372B2 (en) * | 2000-08-03 | 2003-11-06 | Canon Kabushiki Kaisha | Combined control and data pipeline path in computer graphics system |
US7676588B2 (en) * | 2001-10-05 | 2010-03-09 | International Business Machines Corporation | Programmable network protocol handler architecture |
US7072970B2 (en) * | 2001-10-05 | 2006-07-04 | International Business Machines Corporation | Programmable network protocol handler architecture |
US10776047B2 (en) * | 2018-08-30 | 2020-09-15 | Micron Technology, Inc. | Memory characteristic based access commands |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3875391A (en) * | 1973-11-02 | 1975-04-01 | Raytheon Co | Pipeline signal processor |
US4025771A (en) * | 1974-03-25 | 1977-05-24 | Hughes Aircraft Company | Pipe line high speed signal processor |
US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
-
1982
- 1982-10-22 EP EP82109783A patent/EP0078034B1/en not_active Expired
- 1982-10-22 EP EP85110111A patent/EP0176712B1/en not_active Expired - Lifetime
- 1982-10-22 US US06/436,130 patent/US4594653A/en not_active Expired - Lifetime
- 1982-10-22 DE DE8282109783T patent/DE3275139D1/en not_active Expired
- 1982-10-22 DE DE8585110111T patent/DE3280281D1/en not_active Expired - Lifetime
- 1982-10-22 DE DE8585110112T patent/DE3280280D1/en not_active Expired - Lifetime
- 1982-10-22 EP EP85110112A patent/EP0172522B1/en not_active Expired - Lifetime
-
1985
- 1985-12-12 US US06/808,192 patent/US4674034A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0176712B1 (en) | 1991-01-02 |
US4674034A (en) | 1987-06-16 |
EP0176712A3 (en) | 1987-04-22 |
EP0172522A3 (en) | 1987-05-06 |
DE3280280D1 (en) | 1991-02-07 |
EP0078034B1 (en) | 1987-01-14 |
EP0078034A1 (en) | 1983-05-04 |
EP0176712A2 (en) | 1986-04-09 |
EP0172522A2 (en) | 1986-02-26 |
DE3280281D1 (en) | 1991-02-07 |
DE3275139D1 (en) | 1987-02-19 |
US4594653A (en) | 1986-06-10 |
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