JPS58122694A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS58122694A JPS58122694A JP57005664A JP566482A JPS58122694A JP S58122694 A JPS58122694 A JP S58122694A JP 57005664 A JP57005664 A JP 57005664A JP 566482 A JP566482 A JP 566482A JP S58122694 A JPS58122694 A JP S58122694A
- Authority
- JP
- Japan
- Prior art keywords
- points
- information
- electrodes
- current
- inelastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5664—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Read Only Memory (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は非弾性トンネル効果を利用した記憶装置に関
する◎
発明の技術的背景
第1図は弾性トンネル接合の構造を示すもので、Jlは
アルミニウムよシなる電極導体、12はAj20 、よ
りなる絶縁体、13はpbよリなる電極導体である。こ
のようなトンネル接合において両電極導体JJ,JJ間
に電圧を印加した時のバンドダイヤグラムを第2図に示
す.w。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device using an inelastic tunnel effect◎ Technical background of the invention Fig. 1 shows the structure of an elastic tunnel junction, where Jl is an electrode conductor made of aluminum, 12 is an insulator made of Aj20, and 13 is an electrode conductor made of pb. Figure 2 shows a band diagram when voltage is applied between both electrode conductors JJ and JJ in such a tunnel junction. lol.
2図に示すように電圧を印加すると右側w極の電子が左
側へ弾性トンネル効果により移動し電流が流れる。この
時の電圧−電流特性を第3図に示す。第3図において、
電圧に灼する”/dV特性は破線に示すようになる。従
って第1図に示したように1[r出御電流特性は放物線
状となる。As shown in Figure 2, when a voltage is applied, the electrons at the right w pole move to the left due to the elastic tunnel effect, causing a current to flow. The voltage-current characteristics at this time are shown in FIG. In Figure 3,
The "/dV characteristic caused by the voltage is as shown by the broken line. Therefore, as shown in FIG. 1, the 1[r output current characteristic becomes parabolic.
ところで、第1図のようなトンネル接合は弾性トンネル
効果を利用しているもので、電圧1l流特性は連続的に
変化する。By the way, the tunnel junction as shown in FIG. 1 utilizes the elastic tunnel effect, and the voltage 1l flow characteristics change continuously.
背景技術の問題点
しかし、このような弾性トンネル効果會利用して記憶装
置を作ることはできなかった。Problems with the Background Art However, it has not been possible to create a storage device using such an elastic tunnel effect.
発明の目的
この発明は上記の点に鑑みてなされたもので、その目的
は非弾性トンネル効果を利用した記憶装置iltを提供
することにある。Object of the Invention The present invention has been made in view of the above points, and its object is to provide a storage device ilt that utilizes the inelastic tunnel effect.
発明の概暮
両電極をそれぞれ行リ列方向に配置し、これらの交点を
非弾性トンネル接合として、上側の電極を付ける以前に
その交点となる用足の位置に何らかの物質を添加する拳
で情報を蓄え、その読み出しは所定の電圧で電流の急増
がおこるかおこらないかで“有り”無し”を判定してい
る。Summary of the invention: Both electrodes are arranged in the row and column direction, and the intersection of these is used as an inelastic tunnel junction. Before attaching the upper electrode, information is generated by adding some substance to the position of the foot that is the intersection. is stored, and its readout determines whether it is present or absent based on whether a sudden increase in current occurs or not at a predetermined voltage.
発明の実施例
以下、図面全参照してこの発明の−!!施例を説明する
。第4図において、2ノはアルミニウムよりなる電極導
体、22はυ203よシなる絶縁体、23FiPbj#
)なる電極導体である。この絶縁体22KId例えばベ
ンゼン、安息香酸等の冷加物質24が付加されている。EXAMPLES OF THE INVENTION Hereinafter, with reference to all the drawings, -! ! An example will be explained. In Fig. 4, 2 is an electrode conductor made of aluminum, 22 is an insulator such as υ203, and 23FiPbj#
) is the electrode conductor. A cooling substance 24 such as benzene or benzoic acid is added to this insulator 22KId.
!4図のような構造のバンドダイヤグラムIIi第5図
に示す。! A band diagram IIi of the structure shown in FIG. 4 is shown in FIG.
第5図において、電圧全接合に添加した物質の励起モー
ド以上にすると、図の実線で描いたようにこのモードを
励起してトンネルするプロセスも加わるので、電流が増
大するにの場合におけるv−1曲線、及びその微分した
曲#を第6図に示しておく。第6図の%性曲IiMt第
3図の特性1絢を比軟すると、1107/、のバイアス
で電流が急増する。この場合、バイアス値は肉情電極の
種類によらない。ここで、hωは励起モードのエネルギ
ーである。例えば、添、加物賀がベンゼン、安息香酸の
場合0.36V、0.4Vにおいて電流急増がおこる。In Fig. 5, when the voltage is increased above the excitation mode of the substance added to the entire junction, the process of exciting this mode and tunneling is added as shown by the solid line in the figure, so when the current increases, v - 1 curve and its differentiated song # are shown in FIG. When the characteristic curve IiMt in FIG. 6 is compared to the characteristic 1 in FIG. 3, the current increases rapidly at a bias of 1107/. In this case, the bias value does not depend on the type of sensual electrode. Here, hω is the energy of the excitation mode. For example, when the additive is benzene or benzoic acid, a sudden increase in current occurs at 0.36V and 0.4V.
第7図に上記した非弾性トンネル々j果奮利用した記憶
装置を示す。図において、31〜35はそれぞれ行方向
に配列されたw′極で、例えは−フルミニラムよりなる
。また41〜45は夕1jh向に配列された電極で紹!
えばpbよりなる。そして、行方向に配列された電極と
夕1[方向に配夕I]された篭、極との交点に介在する
絶縁物に上記した添加物質を付加した場合にはその添加
物−1七の励起モードのエネルギーに対応するバイアス
を加えたときに電流急増が起こる。このようにして冷加
物負會付加したことV(よる上すじ鋤rncQ−)急増
を検出することにより、行方向の電極と夕IJ方向の電
極との交点に1ビツトの情報がある5かないか検出され
る。実際問題としてにdI/dVh。FIG. 7 shows a storage device that makes full use of the above-mentioned inelastic tunnels. In the figure, 31 to 35 are w' poles arranged in the row direction, and are made of, for example, -fulminilam. Also, 41 to 45 are introduced with electrodes arranged in the evening direction!
For example, it consists of pb. When the above-mentioned additive substance is added to the insulator interposed at the intersection of the electrodes arranged in the row direction and the baskets and poles arranged in the direction, A current surge occurs when a bias corresponding to the energy of the excitation mode is applied. In this way, by detecting a sudden increase in V (resulting in the upper stroke rncQ-) due to the addition of the cold material, it is possible to detect whether there is 1-bit information at the intersection of the row direction electrode and the direction IJ direction electrode. detected. As a practical matter, dI/dVh.
検出するようにしても良い。It may also be detected.
また、交点に介在する絶縁物に付加する両肌物質を2種
類以上とすれば、電流の急増箇所は2ケ所以上となるた
め、交点に2ビ、トリ上の情報を蓄えることができる。Furthermore, if two or more types of skin substances are added to the insulators interposed at the intersection, there will be two or more locations where the current increases sharply, so it is possible to store 2-bi and 3-level information at the intersection.
発明の効果
以上詳述したようKこの発明によれに1異なるエネルギ
ーの励起モードをもつ数種の物質會選べば行9列方向の
配線数を変える事なく、交差点数に更に添加物質の種類
数を掛けただけの多量の情報保持を可能とすることがで
きる。Effects of the Invention As detailed above, by selecting several types of materials having excitation modes of different energies, this invention can increase the number of intersections and the number of types of additive materials without changing the number of wires in the row and nine column directions. It is possible to store a large amount of information multiplied by .
wIJ1図は弾性トンネル接合の構造をポす1弟2図は
バンドダイヤグラムを示す図、第3図は電圧−電流゛%
性を示す凶、第4図は非弾性トンネル接合の構造を示す
図、第5図はバンドダイヤグラムを示す図、第6図Fi
亀、圧−電流特性を示す図11第7図はこの発明に係る
記憶装置を示す図である。
11.13,21.23・・・電極導体、12゜22・
・・絶縁体、24・・・添加物質 31〜35゜41〜
45・・・電極。
第1図
第2図
L−1)−J
第3図
第4図Figure 1 shows the structure of the elastic tunnel junction, Figure 2 shows the band diagram, and Figure 3 shows the voltage-current ratio.
Fig. 4 shows the structure of an inelastic tunnel junction, Fig. 5 shows the band diagram, Fig. 6 Fi
11 and 7, which show piezoelectric current characteristics, are diagrams showing a memory device according to the present invention. 11.13, 21.23... Electrode conductor, 12°22.
...Insulator, 24...Additive substance 31~35°41~
45...electrode. Figure 1 Figure 2 L-1)-J Figure 3 Figure 4
Claims (1)
有の励起モードをもつ1あるいは複数種の物質を添加し
、交互部に1あるいは複数種の情報を記憶するようKし
たことを特徴とする記憶装置。M) Adding one or more kinds of substances having a unique excitation mode to the alternating parts of row lines and column lines arranged in a box shape, and storing one or more kinds of information in the alternating parts. A storage device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57005664A JPS58122694A (en) | 1982-01-18 | 1982-01-18 | Storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57005664A JPS58122694A (en) | 1982-01-18 | 1982-01-18 | Storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58122694A true JPS58122694A (en) | 1983-07-21 |
Family
ID=11617366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57005664A Pending JPS58122694A (en) | 1982-01-18 | 1982-01-18 | Storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58122694A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4205044A1 (en) * | 1991-02-19 | 1992-08-20 | Mitsubishi Electric Corp | Masked read-only memory array integrated with CMOS integrated circuit - uses tunnel-effect through an oxide between bit-line and word-line to indicate the stored logic status |
US8061289B2 (en) | 2006-03-29 | 2011-11-22 | Jon Khachaturian | Marine lifting apparatus |
US8985040B2 (en) | 2006-12-13 | 2015-03-24 | Jon Khachaturian | Marine lifting apparatus |
-
1982
- 1982-01-18 JP JP57005664A patent/JPS58122694A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4205044A1 (en) * | 1991-02-19 | 1992-08-20 | Mitsubishi Electric Corp | Masked read-only memory array integrated with CMOS integrated circuit - uses tunnel-effect through an oxide between bit-line and word-line to indicate the stored logic status |
US5464989A (en) * | 1991-02-19 | 1995-11-07 | Mitsubishi Denki Kabushiki Kaisha | Mask ROM using tunnel current detection to store data and a method of manufacturing thereof |
DE4205044C2 (en) * | 1991-02-19 | 1996-07-11 | Mitsubishi Electric Corp | Read-only memory (mask ROM) and method for its production |
US5580809A (en) * | 1991-02-19 | 1996-12-03 | Mitsubishi Denki Kabushiki Kaisha | Method of making a mask ROM using tunnel current detection to store data |
US8061289B2 (en) | 2006-03-29 | 2011-11-22 | Jon Khachaturian | Marine lifting apparatus |
US9604710B2 (en) | 2006-03-29 | 2017-03-28 | Jon Khachaturian | Marine lifting apparatus |
US10543890B2 (en) | 2006-03-29 | 2020-01-28 | Versabar, Inc. | Marine lifting apparatus |
US11345452B2 (en) | 2006-03-29 | 2022-05-31 | Versabar, Inc. | Marine lifting apparatus |
US8985040B2 (en) | 2006-12-13 | 2015-03-24 | Jon Khachaturian | Marine lifting apparatus |
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