JPS58121683A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS58121683A JPS58121683A JP57003588A JP358882A JPS58121683A JP S58121683 A JPS58121683 A JP S58121683A JP 57003588 A JP57003588 A JP 57003588A JP 358882 A JP358882 A JP 358882A JP S58121683 A JPS58121683 A JP S58121683A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- layer
- gate structure
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は70一テイングゲート形不揮発性メモリに用
いる二重ゲートの電界効果トランジスタ構造の半導体索
子からなる集積回路装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an integrated circuit device comprising a semiconductor element having a double-gate field effect transistor structure used in a 70-bit gate type nonvolatile memory.
#I1図(a)〜(0)は従来の製造方法の主要工種段
階における状態を示す断面図で、まず#I1図k)K示
すようにシリコン基板(110票子間分離酸化膜(7)
で分離された部分の表面上の所定部分にゲート酸化@(
2)e下層ポリシリコン層(8)9層間酸化111(4
)、および上層ポリシリコン層(旬が順次相重なって形
成され、これらをマスクとしてソース、ドレイン領域(
6)が拡散法またはイオン注入法で形成される。#I1 Figures (a) to (0) are cross-sectional views showing the main steps of the conventional manufacturing method.
Gate oxidation @(
2) e lower polysilicon layer (8) 9 interlayer oxidation 111 (4
), and the upper polysilicon layer (layers) are formed sequentially overlapping each other, and using these as a mask, the source and drain regions (
6) is formed by a diffusion method or an ion implantation method.
つづいてソース、ドレイン領域(6)および上層ポリシ
リコン層(制御ゲー))(5Jへのそれぞれ配線層を形
成するのであるが、そのために、第1図(1))に示す
ように配線絶縁層(8」を形成し、つづいて、その上に
第1図(Q)に示すようにレジスト層(9)を形成した
後、配線層を形成すべきソース、ドレイン領域(6)お
よび制御ゲート(5)の直上部分に開孔−を形成し、こ
のレジスト層(9)をマスクとして開孔(7)に相当す
る部分の配線絶縁層(8)に選択エツチングを施してコ
ンタクトホールな形成し、その部分に配線層(川を形成
する。Next, wiring layers are formed for the source and drain regions (6) and the upper polysilicon layer (control gate) (5J), but for this purpose, as shown in FIG. 1 (1), a wiring insulating layer is formed. (8), and then a resist layer (9) is formed thereon as shown in FIG. 5) an opening is formed directly above the opening, and using this resist layer (9) as a mask, selective etching is performed on the wiring insulating layer (8) in a portion corresponding to the opening (7) to form a contact hole; Form a wiring layer (river) in that part.
ところが、上記従来の方法では、開孔四を形成するため
のマスク合わせ作業がある丸め、開孔−すなわち配線層
(1υと素子間分離酸化膜(7)との距離A、配線層(
lりの幅B、および配線層(lυと制御ゲート(5)と
の距@Cの設定に十分配慮が必要であシ、通常人は1μ
m、 Bは3μm、 aは2μmが必要である。However, in the above-mentioned conventional method, there is rounding, which involves mask alignment work to form the openings 4, the distance A between the openings - that is, the wiring layer (1υ) and the inter-element isolation oxide film (7), and the wiring layer (
It is necessary to take sufficient consideration in setting the width B of the wire and the distance @C between the wiring layer (lυ and the control gate (5).
m and B are required to be 3 μm, and a is required to be 2 μm.
従って、制御ゲート(5)と素子量分111&化膜(7
)との間の必要距離は最小6μmとなり、大集積化の丸
めのパターンの微細化の重大な障害となっている。Therefore, the control gate (5) and the element amount 111 & chemical film (7)
) is a minimum of 6 μm, which is a serious obstacle to miniaturization of round patterns for large scale integration.
この発明は以上のような点に鑑みてなされたもので2重
ゲート構造を形成後、マスクを用いることなく2重ゲー
ト部外面に酸化膜を形成して、自動的にソース、ドレイ
ンへのコンタクトホールを形成させるようにすることに
よって、ゲートと素子量分llI!#化膜との閾の必要
距離を小ならしめ大集積化の容易な製造方法を提供する
ことを目的としている。This invention was made in view of the above points, and after forming a double gate structure, an oxide film is formed on the outer surface of the double gate part without using a mask, and contacts to the source and drain are automatically established. By forming holes, the gate and element amount llI! It is an object of the present invention to provide a manufacturing method that facilitates large-scale integration by reducing the required distance between the threshold and the #-coated film.
!!2図(a)〜(・)はこの発明の一実施例の主要上
根段階における状態を示す断面図である。まず、第2図
(、)に示すように、通常の選択酸化法によってシリコ
ン基板電11上に素子関分離酸化展(7)を形成した後
に、膜厚700Aのゲート酸化膜+2) I II厚3
500Aの下層ポリシリコン層(3)、膜厚1200人
の層ri41m化膜(4)および膜厚3500Aの上層
ポリシリコン層(6)を周知の熱酸化法および気相成長
法並びに周知のレジストマスクα匂を用いたエツチング
法によって形成する。両ポリシリコン層(3)および(
5)にはリンが拡散され、そのシート抵抗は20010
である。その後、酸素プラズマによるエツチングによっ
てレジストマスク(l乃を除去し、第2図(b)に示す
ように600”Cの温度、水蒸気圧8kg10m”の雰
囲気中での高圧酸化法によって、シリコン基板1110
表面に50OAの厚さの酸化膜を形成させる。第3図は
このときの酸化温度とシート抵抗20Q10のポリシリ
コン層上に形成される熱酸化膜の膜厚との関係を示す曲
線で、上記条件ではポリシリコン層上には約3200A
の厚さの酸化膜が形成される。従って、第2図(1))
に示し友ように、シリコン基板(11の上には薄く(5
00A)、両ポリシリコン層(3)および(5)の周辺
は厚< (3500A)酸化膜01で被覆されることに
なる。! ! FIGS. 2(a) to 2(•) are cross-sectional views showing the state of an embodiment of the present invention at the main upper root stage. First, as shown in FIG. 2(, ), after forming a device isolation oxide film (7) on a silicon substrate electrode 11 by a normal selective oxidation method, a gate oxide film with a thickness of 700 A + 2) I II thickness is formed. 3
A 500A lower polysilicon layer (3), a 1200A RI41M film (4), and a 3500A upper polysilicon layer (6) were formed using well-known thermal oxidation methods and vapor phase growth methods, as well as well-known resist masks. Formed by an etching method using alpha odors. Both polysilicon layers (3) and (
5) is diffused with phosphorus, and its sheet resistance is 20010
It is. Thereafter, the resist mask (l) is removed by etching with oxygen plasma, and as shown in FIG.
An oxide film with a thickness of 50 OA is formed on the surface. Figure 3 is a curve showing the relationship between the oxidation temperature at this time and the thickness of the thermal oxide film formed on the polysilicon layer with a sheet resistance of 20Q10.
An oxide film with a thickness of . Therefore, Figure 2 (1))
As shown in FIG.
00A), the peripheries of both polysilicon layers (3) and (5) are covered with an oxide film 01 with a thickness < (3500A).
つづいて、へ7ツ化三炭素(a3?8)ガスを用いて平
行平板形エツチング装置でプラズマエツチングを行なう
と、1分間に45OAの厚さだけ酸化膜−がエツチング
され、1分15秒のエツチング盛ζよって、第2図(C
)に示すように、シリコン基板(1)上の酸化膜は除去
してポリシリコン層(3) 、 (5)力)らなる二層
ゲート周辺の酸化膜(13a)は約2フOOAの厚さに
残すことができ、ゲート周辺をうま(被覆することがで
きる。その後、 5XIO”/am”のa度にヒ票をシ
リコン基板(1)にイオン注入法で注入し、105πの
温度で窒素(Nl)中で40分アニールを行ない、ソー
ス、ドレイン領域(6)を形成する。次に、1に2図(
d)に示すようにこの構成体の全上面にス/(ツタリン
グ法でアルミニウムシリコン(At−813合金層−を
形成し、つづいて、#I2図(・)に示すようにとのA
t−81合金層α彎にバターニングを施し、ゲート部で
分離してソースおよびドレイン配線層(14a)!:t
ル。以上のように、この実施例の方法ではソースおよび
ドレイン領域(6)への配線層(違)の形成に従来例の
場合のようなマスクを用いて開孔を形成する必要がなく
、素子間分離酸化膜(7)と制御ゲート(5)との距離
は素子間分離酸化[(7)形成時のマスクと制御ゲート
(5)形成時のマスクとのマスク合わせ精度2μmに二
層ゲート周辺の酸化[(13a)の厚さの精度を加えて
も3μmにすることができる。Next, when plasma etching was performed using a parallel plate type etching device using tricarbon tricarbonate (A3-8) gas, the oxide film was etched to a thickness of 45 OA per minute, and the oxide film was etched to a thickness of 45 OA per minute. According to the etching pattern ζ, Fig. 2 (C
), the oxide film on the silicon substrate (1) is removed, and the oxide film (13a) around the two-layer gate consisting of the polysilicon layer (3) and (5) is approximately 2 FOA thick. It is possible to leave the area in the silicon substrate (1) and cover the area around the gate with ion implantation at a temperature of 5XIO"/am", followed by nitrogen injection at a temperature of 105 Annealing is performed for 40 minutes in (Nl) to form source and drain regions (6). Next, Figures 1 and 2 (
As shown in Fig. d), an aluminum silicon (At-813 alloy layer) is formed on the entire upper surface of this structure by the tuttering method, and then an A layer is formed as shown in Figure #I2 (-).
The t-81 alloy layer α is patterned and separated at the gate portion to form a source and drain wiring layer (14a). :t
Le. As described above, in the method of this embodiment, there is no need to use a mask to form openings as in the conventional method when forming wiring layers (different layers) in the source and drain regions (6), and The distance between the isolation oxide film (7) and the control gate (5) is determined by the mask alignment accuracy of 2 μm between the mask for forming the isolation oxide film (7) and the mask for forming the control gate (5), and the area around the double layer gate. Even if the accuracy of the thickness of oxidation [(13a) is added, the thickness can be reduced to 3 μm.
なお、上記実施例ではメモリ素子部分のみを図示してい
るが、制御ゲート(5)への配線層は、このメモリ素子
部分ではなく、上層ポリシリコン層(5)を引伸ばして
集積回路装置の周辺に形成した。このための周辺部での
ポリシリコン層(5)へ接続する念めの開孔はマスクを
用いたが、このマスク合わせはメモリ素子部には無関係
に行なえるので、素子の微細化に悪影響は与えない。更
に酸化膜−の形成には高圧酸化法を用いたが、この方法
に限らず他の方法で形成してもよい。In the above embodiment, only the memory element part is shown, but the wiring layer to the control gate (5) is not connected to the memory element part, but by stretching the upper polysilicon layer (5) of the integrated circuit device. formed around it. For this purpose, a mask was used to make the holes connected to the polysilicon layer (5) in the peripheral area, but this mask alignment can be done regardless of the memory element area, so there is no negative effect on the miniaturization of the element. I won't give it. Furthermore, although the high-pressure oxidation method was used to form the oxide film, it is not limited to this method and may be formed by other methods.
以上説明し念ように、この発明ではシリコン表面とポリ
シリコン表面との酸化膜の形成速度の差異を利用して二
重ゲート構成体の外面にマスクを用いることなく酸化膜
を形成して、自動的にソース領域およびドレイン領域へ
のコンタクトホールを形成させるようにしたので、マス
ク合わせのための寸法余裕を必要とせず、素子パターン
の微少化が=J能にな9、大集積度が達成できる。As explained above, in this invention, an oxide film is automatically formed on the outer surface of a double gate structure without using a mask by utilizing the difference in the formation rate of an oxide film between a silicon surface and a polysilicon surface. Since contact holes are formed to the source and drain regions automatically, there is no need for dimensional margins for mask alignment, miniaturization of device patterns is possible9, and a large degree of integration can be achieved. .
第1図(a)〜(Q)は従来の製造方法の主要工程段階
における状態を示す断面図、I!2図(a)〜(e)は
この発明の一実施例の主要工tmR階における状態を示
す断面図、第3図は高圧酸化法でシリコン基板上に50
OAの熱威化膜を形成したときのシート抵抗20Ω/口
のポリシリコン上に形成される熱酸化膜の膜厚と酸化@
度との関係を示す曲線図である。
図において、【1)はシリコン基板、(2)はゲート績
化膜、(3)は下層ポリシリコン層、(4)は層間酸化
膜、(51は上層ポリシリコン層、(6)はドレインお
よびソース領域、(71は菓子量分ll11酸化膜、0
1 * (13”)は酸化膜、幀は導電層、(違)はソ
ースおよびドレイン配線層である。
なお、図中同一符号は同一ま次は相当部分を示す。
代理人 葛野信−(外1名)
第1図
第2図
裔妃警紗FIGS. 1(a) to (Q) are cross-sectional views showing the main process steps of the conventional manufacturing method. Figures 2 (a) to (e) are cross-sectional views showing the state of the main construction tmR floor of one embodiment of the present invention, and Figure 3 is a
Thickness and oxidation of thermally oxidized film formed on polysilicon with sheet resistance of 20Ω/hole when thermally oxidized film of OA is formed
It is a curve diagram showing the relationship with degree. In the figure, [1] is the silicon substrate, (2) is the gate layer, (3) is the lower polysilicon layer, (4) is the interlayer oxide film, (51 is the upper polysilicon layer, and (6) is the drain and Source region, (71 is 11 oxide film for sweets, 0
1 * (13") is an oxide film, the ridge is a conductive layer, and (different) is a source and drain wiring layer. In addition, the same reference numerals in the figure indicate the corresponding parts. Agent Shin Kuzuno (external) 1 person) Fig. 1 Fig. 2 Descendant Keisha
Claims (1)
形成される素子との閏を分離する素子間分離酸化膜を形
成する#11の工程、上記シリコン基板の上記素子間分
離酸化膜で囲まれた素子形成領域上の一部にゲート酸化
膜と下層ポリシリコン層と層間酸化膜と上層ポリシリコ
ン層とが順次重なってなるゲート構成体を形成する第2
の工程、上記素子形成領域の上記シリコン基板と上記ゲ
ート構成体との表面を酸化させて上記シリコン基板上に
は薄い酸化膜を上記ゲート構成体表面には厚い酸化膜を
形成する第3の工程、上記第3の工程で形成された酸化
膜に上記シリコン基板上の薄い酸化膜が消失する1度の
グツズ!エツチングを總し上記ゲート構成体表面には酸
化膜を残す第4の工程、上記ゲート構成体をマスクとし
て上記第4の工程で痣出した上記シリコン基板に不純物
を導入して上記ゲート構成体の両側にそれぞれソース領
域およびドレイン領域を形成する第5の工程、上記素子
間分離酸化膜上と上記ソース領域上と上記ゲート構成体
上と上記ドレイン領域上とにわ九って導電層を形成する
$6の工程、及び上記411層を上記ゲート構成体部分
で上記ソース領域側と上記ドレイン領域側とに分割して
それぞれソース配線層およびドレイン配線層とする第〒
の工程を備えたことを特徴とする半導体集積回路装置の
製造方法。(Step #11 of forming an inter-element isolation oxide film on the silicon substrate to isolate the inter-element isolation oxide film from the elements formed on other parts of the silicon substrate, A second gate structure is formed in which a gate oxide film, a lower polysilicon layer, an interlayer oxide film, and an upper polysilicon layer are sequentially overlapped on a part of the element formation region.
a third step of oxidizing the surfaces of the silicon substrate and the gate structure in the element formation region to form a thin oxide film on the silicon substrate and a thick oxide film on the surface of the gate structure; , the thin oxide film on the silicon substrate disappears into the oxide film formed in the third step! a fourth step of etching to leave an oxide film on the surface of the gate structure; using the gate structure as a mask, impurities are introduced into the silicon substrate that has been scratched in the fourth step; a fifth step of forming a source region and a drain region on both sides, forming a conductive layer on the element isolation oxide film, on the source region, on the gate structure, and on the drain region; Step 6, and step 1, in which the 411th layer is divided into the source region side and the drain region side at the gate structure portion to form a source wiring layer and a drain wiring layer, respectively.
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57003588A JPS58121683A (en) | 1982-01-12 | 1982-01-12 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57003588A JPS58121683A (en) | 1982-01-12 | 1982-01-12 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58121683A true JPS58121683A (en) | 1983-07-20 |
Family
ID=11561615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57003588A Pending JPS58121683A (en) | 1982-01-12 | 1982-01-12 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58121683A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5145797A (en) * | 1990-01-30 | 1992-09-08 | Seiko Instruments, Inc. | Method of making semiconductor devices having an implant damage protection film on the gate electrode sidewalls |
-
1982
- 1982-01-12 JP JP57003588A patent/JPS58121683A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5145797A (en) * | 1990-01-30 | 1992-09-08 | Seiko Instruments, Inc. | Method of making semiconductor devices having an implant damage protection film on the gate electrode sidewalls |
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