JPS58115862A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS58115862A JPS58115862A JP21254281A JP21254281A JPS58115862A JP S58115862 A JPS58115862 A JP S58115862A JP 21254281 A JP21254281 A JP 21254281A JP 21254281 A JP21254281 A JP 21254281A JP S58115862 A JPS58115862 A JP S58115862A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- oxide film
- forming
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 45
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000003595 mist Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 abstract description 4
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 238000007788 roughening Methods 0.000 abstract description 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は多結晶シリコンを半導体膜としてなる薄膜トラ
ンジスタに関し、皺多結晶シリコン膜の表面の荒れを防
止し、ゲート膜となるＣＶＤ酸化膜の特性向上を訃→得
る構造を備えた薄膜トランジスタに関する◇
薄膜トランジスタは、高価なシリコン基板上に形成する
半導体素子に比べ、安価なガラス基板上に形成できると
供に、工程数も少なくできる利点を持っている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film transistor using polycrystalline silicon as a semiconductor film, and provides a structure that prevents the surface of the wrinkled polycrystalline silicon film from becoming rough and improves the characteristics of the CVD oxide film that serves as the gate film. Regarding thin film transistors ◇ Compared to semiconductor elements formed on expensive silicon substrates, thin film transistors have the advantage of being able to be formed on inexpensive glass substrates and requiring fewer steps.
特に透明基板上に薄膜トランジスタアレイを形成し、液
晶ディスプレイを構成したフラットパネル等では、裏面
に反射率の高い反射板をセットすることができ、コント
ラストの良い表示を得ることができるので多くの研がさ
れている。In particular, for flat panels that have a thin film transistor array formed on a transparent substrate to form a liquid crystal display, a reflector plate with high reflectance can be set on the back side, and a display with good contrast can be obtained, which requires a lot of polishing. has been done.
第１図（ａ）（ｂ）（ｃ）を用いて従来の薄膜トランジ
スタの構造を示し、その欠点を述べる。The structure of a conventional thin film transistor will be shown using FIGS. 1(a), 1(b), and 1(c), and its drawbacks will be described.
ガラス基板１上に多結晶シリコン膜の島２を形成し九の
ち、表面を酸化しえものを（ａ） Ｋ示す。次にゲート
電極となる多結晶シリコン膜４を形成する◎さらに弗酸
等によシゲート電極４をマスクにシリコン酸化膜３をエ
ツチング除去し、ソース・ドレイン拡散層５を形成した
ものを（ｂ） Ｋ示す。An island 2 of a polycrystalline silicon film is formed on a glass substrate 1, and the surface is then oxidized as shown in (a) K. Next, a polycrystalline silicon film 4 that will become a gate electrode is formed. ◎ Furthermore, the silicon oxide film 3 is etched away using hydrofluoric acid or the like using the silicate gate electrode 4 as a mask, and a source/drain diffusion layer 5 is formed. (b) Show K.
次に層間絶縁膜６を形成したのちに１コンタクトホール
を間にし、アルミニウムあるいはアルミニウム合金配＠
７を形成する。Next, after forming an interlayer insulating film 6, one contact hole is formed between the aluminum or aluminum alloy layers.
form 7.
第１図（ａ）から分かるように、従来の方式では、多結
晶シリコン膜を熱酸化することにより酸化シリコン表面
が凹凸状１１１になるとともに、酸化シリコン膜と多結
晶シリコン膜の界面も凹凸状態となり、トランジスタ特
性を幾くする。As can be seen from FIG. 1(a), in the conventional method, by thermally oxidizing the polycrystalline silicon film, the silicon oxide surface becomes uneven 111, and the interface between the silicon oxide film and the polycrystalline silicon film also becomes uneven. Therefore, the transistor characteristics are improved.
改善策としては、ゲート膜としてＣＶＤ法による酸化シ
リコン膜を窒素霧囲気中でアニールした絶縁膜を用いる
方法もあるが特性の向上が顕著でない。これはＣＶＤ法
による酸化シリコン膜の特性が、単結晶シリコン膜の熱
酸化膜に比べ充分なものでない結果であり、オン電流の
減少、オフリーク電流の増加につながる。As an improvement measure, there is a method of using an insulating film obtained by annealing a silicon oxide film formed by CVD in a nitrogen mist atmosphere as the gate film, but the improvement in characteristics is not significant. This is a result of the characteristics of the silicon oxide film produced by the CVD method being less satisfactory than that of the thermally oxidized single crystal silicon film, leading to a decrease in on-current and an increase in off-leakage current.
本発明は、この様な従来の欠点を除去したものｉ
であり、その目的とするところは、多結晶シリコン膜
の表面を荒らす事なく、特性の良いゲート酸化膜を提供
することである。The present invention eliminates such conventional drawbacks.
The purpose is to provide a gate oxide film with good characteristics without roughening the surface of the polycrystalline silicon film.
以下第２図（ａ）（ｂ）（ｃ）を用いて本発明の詳細な
説明する。The present invention will be described in detail below using FIGS. 2(a), (b), and (c).
ガラス基板１１上に多結晶シリコン膜の島１２を形成し
たのち、ＣＶＤ法による酸化シリコン膜１３を形成する
。次に酸素群囲気中で熱処理を行なったものを（ａ）に
示す０次にゲート電極となる多結晶シリコン膜１４を形
成する。さらに弗酸傳によシ、ゲート電極１４をマスク
に酸化シリコン膜１３をエツチング除来し、ソース・ド
レイン拡散層１５を形成したものを（ｂ）に示す０次に
層間絶縁膜１６を形成したのちに、コンタクトホールを
開口し、アルミニウムあるいはアルミニウム合金等の配
線１７を形成する。After forming an island 12 of a polycrystalline silicon film on a glass substrate 11, a silicon oxide film 13 is formed by CVD. Next, a polycrystalline silicon film 14, which will become a zero-order gate electrode, is formed by heat treatment in an oxygen group atmosphere, as shown in (a). Furthermore, the silicon oxide film 13 was removed by etching using a hydrofluoric acid solution, using the gate electrode 14 as a mask, and a source/drain diffusion layer 15 was formed, and then an interlayer insulating film 16 was formed as shown in (b). Later, a contact hole is opened and a wiring 17 made of aluminum or aluminum alloy is formed.
第２図（ａ）からも分かる様に多結晶シリコン膜１２を
熱酸化していないので多結晶シリコン膜の表面の凹凸が
ない。さらに、酸素ｍ＃！気中でアニールすることによ
り、ＣｖＤ酸化膜の特性が向上する。As can be seen from FIG. 2(a), since the polycrystalline silicon film 12 is not thermally oxidized, there is no unevenness on the surface of the polycrystalline silicon film. Furthermore, oxygen m#! Annealing in air improves the properties of the CvD oxide film.
熱処理温度は高い程良い特性が得られるが、高い温度で
過乗にアニールすると、ＣｖＤ酸化膜を通して酸素が拡
散され、多結晶シリコン膜１２が酸化されてしまう。多
結晶シリコン膜の表面が酸化される事により表面が凹凸
状態になり、直接多結晶シリコン膜を熱酸化した場合と
同じ結果に表り良い特性が得られない。The higher the heat treatment temperature, the better the characteristics can be obtained, but if excessive annealing is performed at a high temperature, oxygen will be diffused through the CvD oxide film and the polycrystalline silicon film 12 will be oxidized. As the surface of the polycrystalline silicon film is oxidized, the surface becomes uneven, resulting in the same result as when directly thermally oxidizing the polycrystalline silicon film, and good characteristics cannot be obtained.
本発明によるゲート酸化膜形成方法によれば、ＣＶＤ法
による酸化シリコン膜を酸素群囲気中でアニールする事
によシ、多結晶シリコン膜の表面を荒らすことなく、又
、熱酸化膜と同等の特性の良いゲート膜を形成すること
ができる。According to the method for forming a gate oxide film according to the present invention, by annealing a silicon oxide film formed by the CVD method in an oxygen group atmosphere, the surface of the polycrystalline silicon film is not roughened, and the film is equivalent to a thermal oxide film. A gate film with good characteristics can be formed.
る。Ru.
第２図は本発明による実施例を示す断面図である。FIG. 2 is a sectional view showing an embodiment according to the present invention.
図中１．１１はガラス基板、２，１．２はトランジスタ
となる多結晶シリコンの島、３．１！！はゲート酸化膜
、４．１４はゲート電極、５．１５はソースあるいはド
レイン、６．１６は層間絶縁膜７．１７はアルミニウム
酸線である・
以上In the figure, 1.11 is a glass substrate, 2 and 1.2 are polycrystalline silicon islands that will become transistors, and 3.1! ! is the gate oxide film, 4.14 is the gate electrode, 5.15 is the source or drain, 6.16 is the interlayer insulating film 7.17 is the aluminum oxide wire.
Claims (1)
、前記多結晶シリコン膜上１２ＣＶＤ法による酸化シリ
コン膜を形成する工１と、引き続き、酸素霧囲気中で熱
処理する工程と、引き続きゲート電極となる金属若しく
は半一体膜を形成する工程と、前記金属若しくは半導体
膜をマスクにソース・ドレイン拡散を行なう工程と、引
き続き層間絶縁膜を形成する工程と、層間絶縁膜上に金
属配線を被害してリース電極、ゲート電極を形成する工
程とを具備してなる薄膜トランジスタの製造方法・Step 1 of forming islands of a polycrystalline silicon film on an insulating substrate, step 1 of forming a silicon oxide film on the polycrystalline silicon film by the CVD method, followed by a step of heat treatment in an oxygen mist atmosphere, and then a gate step. A process of forming a metal or semi-integral film to serve as an electrode, a process of performing source/drain diffusion using the metal or semiconductor film as a mask, a process of subsequently forming an interlayer insulating film, and a process of damaging metal wiring on the interlayer insulating film. A method for manufacturing a thin film transistor, comprising a step of forming a lease electrode and a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21254281A JPS58115862A (en) | 1981-12-28 | 1981-12-28 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21254281A JPS58115862A (en) | 1981-12-28 | 1981-12-28 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58115862A true JPS58115862A (en) | 1983-07-09 |
Family
ID=16624397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21254281A Pending JPS58115862A (en) | 1981-12-28 | 1981-12-28 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58115862A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59115564A (en) * | 1982-12-23 | 1984-07-04 | Seiko Instr & Electronics Ltd | Thin film transistor |
| WO1985004731A1 (en) * | 1984-04-09 | 1985-10-24 | Hosiden Electronics Co., Ltd. | Liquid crystal display element and a method of producing the same |
| US5506461A (en) * | 1993-03-05 | 1996-04-09 | Mitsuba Electric Manufacturing Co., Ltd. | Brush assembly structure for motor |
-
1981
- 1981-12-28 JP JP21254281A patent/JPS58115862A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59115564A (en) * | 1982-12-23 | 1984-07-04 | Seiko Instr & Electronics Ltd | Thin film transistor |
| JPH0546105B2 (en) * | 1982-12-23 | 1993-07-13 | Seiko Instr & Electronics | |
| WO1985004731A1 (en) * | 1984-04-09 | 1985-10-24 | Hosiden Electronics Co., Ltd. | Liquid crystal display element and a method of producing the same |
| US5506461A (en) * | 1993-03-05 | 1996-04-09 | Mitsuba Electric Manufacturing Co., Ltd. | Brush assembly structure for motor |
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