JPS5811357U - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPS5811357U JPS5811357U JP10351181U JP10351181U JPS5811357U JP S5811357 U JPS5811357 U JP S5811357U JP 10351181 U JP10351181 U JP 10351181U JP 10351181 U JP10351181 U JP 10351181U JP S5811357 U JPS5811357 U JP S5811357U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- output circuit
- latch
- output
- output data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は集積回路の出力回路の従来例を示すブロック図
、第２図は本考案に係る出力回路の一実施例を示すブロ
ック図、第３図は第２図に示した実施例の動作を説明す
るタイミングチャートである。−パ
゛ １・・・出力レジスタ、２・・・クロック信号発生
回路、３・・・ゲート回路１，４，５・・・出力バッフ
ァ回路、６゜７・・・ラチ回路、８・・・ラッチクロッ
ク信号発生回路。Fig. 1 is a block diagram showing a conventional example of an output circuit of an integrated circuit, Fig. 2 is a block diagram showing an embodiment of an output circuit according to the present invention, and Fig. 3 is an operation of the embodiment shown in Fig. 2. 2 is a timing chart illustrating. 1... Output register, 2... Clock signal generation circuit, 3... Gate circuits 1, 4, 5... Output buffer circuit, 6°7... Rati circuit, 8... Latch clock signal generation circuit.
Claims (2)
ク信号に同期して出力する出力回路において、該出力デ
ータが加えられるｎ個のラッチ回路と、周波数力４ｆｃ
／ｎでかつそれぞれ位相の異なるｎ個のラッチクロック
信号を前記同期クロック信号に同期して形成するラッチ
クロック信号発生回路とを具え、該ｎ個の？ツチクロツ
ク信号をそれぞれ前記ｎ個のラッチ回路に加え、前記出
力データをｎ個の出力′ラインにデマルチプレクスする
ことを特徴とする出力回路。(1) In an output circuit that outputs output data in synchronization with a synchronous clock signal of a predetermined frequency fc, there are n latch circuits to which the output data is applied, and a frequency power 4fc.
a latch clock signal generation circuit that generates n latch clock signals of /n and each having a different phase in synchronization with the synchronous clock signal; An output circuit characterized in that a clock signal is applied to each of the n latch circuits, and the output data is demultiplexed to n output lines.
位相力ｒ３６０’ ／ｎづつ異なる実用新案登録請求の
範囲第（１）項記載の出力回路。(2) The output circuit according to claim (1), wherein the n latch clock signals each have a different phase power r360'/n.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10351181U JPS5811357U (en) | 1981-07-13 | 1981-07-13 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10351181U JPS5811357U (en) | 1981-07-13 | 1981-07-13 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5811357U true JPS5811357U (en) | 1983-01-25 |
Family
ID=29898122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10351181U Pending JPS5811357U (en) | 1981-07-13 | 1981-07-13 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811357U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09238128A (en) * | 1988-04-01 | 1997-09-09 | Digital Equip Corp <Dec> | Digital system stabilized in data transfer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50122815A (en) * | 1974-03-11 | 1975-09-26 |
-
1981
- 1981-07-13 JP JP10351181U patent/JPS5811357U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50122815A (en) * | 1974-03-11 | 1975-09-26 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09238128A (en) * | 1988-04-01 | 1997-09-09 | Digital Equip Corp <Dec> | Digital system stabilized in data transfer |
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