JPS58112328A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58112328A
JPS58112328A JP57184045A JP18404582A JPS58112328A JP S58112328 A JPS58112328 A JP S58112328A JP 57184045 A JP57184045 A JP 57184045A JP 18404582 A JP18404582 A JP 18404582A JP S58112328 A JPS58112328 A JP S58112328A
Authority
JP
Japan
Prior art keywords
heattreated
atmosphere
implanted
gaas
pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57184045A
Other languages
Japanese (ja)
Inventor
Takeshi Konuma
小沼 毅
Toshio Sugawa
俊夫 須川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57184045A priority Critical patent/JPS58112328A/en
Publication of JPS58112328A publication Critical patent/JPS58112328A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To manufacture the semiconductor device with excellent electric properties and remarkable mobility by a method wherein ion implanted GaAs is heattreated in As atmosphere. CONSTITUTION:The semi-insulated GaAs with specific resistance exceeding 10<6>OMEGA-cm added to chrome is heattreated in vacuum at 700 deg.C for three hours to form As holes. The As holes may be formed by means of heattreating the GaAs in gallium atmosphere or forming crystal in the Ga excessive status. Then sulfur is implanted into a substrate formed of As holes as mentioned so far and the substrate is heattreated in As atmosphere with As pressure of 120mm.Hg at 800 deg.C for 30min. The As pressure may be selected by means of changing temperature of the adopted metallic As. It was detected that the effective movability of this sample is 4,500cm<2>/V.sec while in case the sample is heattreated utilizing Si3N4 film as a protective film without applying the As pressure, the effective movability is 4,100cm<2>/V.sec subject to almost no fluctuation of activation ratio.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法、特に化合物半導体基板
におけるイオン注入に関し、イオン注入したイオン注入
層の電気的特性を良好ならしめる半導体装置の製造方法
を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, particularly ion implantation in a compound semiconductor substrate, and a method for manufacturing a semiconductor device that improves the electrical characteristics of an ion-implanted layer into which ions are implanted. This is what we provide.

従来例の構成とその問題点 イオン注入を行った場合、一般に半導体基板に格子不整
が生じ、形成された半導体装置の電気的特性が劣化する
。即ち注入イオンは基板を構成する原子との衝突により
、結晶の格子点にある原子がはじきだされ、空格子と格
子間原子を形成する。
Conventional Structures and Problems When ion implantation is performed, lattice misalignment generally occurs in the semiconductor substrate, degrading the electrical characteristics of the formed semiconductor device. That is, the implanted ions collide with atoms constituting the substrate, and atoms at lattice points of the crystal are ejected, forming vacancies and interstitial atoms.

一般嬉注入された不純物原子は格子間をほとんど占める
ため、熱処理によって格子間原子を所定の格子位置に置
換し、欠陥を除去して電気的特性の良好な半導体装置を
得ようとしている。
In general, the implanted impurity atoms occupy most of the interstitial spaces, so heat treatment is used to replace the interstitial atoms at predetermined lattice positions and remove defects to obtain a semiconductor device with good electrical characteristics.

イオン注入した化合物半導体の熱処理方法としては、シ
リコン酸化膜(S 102 > 、シリコン窒化膜(S
i3N4)等の保護膜でイオン注入した化合物半導ずを
保護して熱処理する方法及び保護膜を用いずに熱処理す
る方法が用いられている。前者の方法はイオン注入した
化合物半導体を3102等の保護膜で保護して熱処理す
るので、保護膜と化合物半導体の熱膨張係数の差による
歪が発生し、結晶欠陥が生ずる。又化合物半導体の構成
元素の保護膜への拡散に伴う化合物半導体表面近傍の化
学量論的組成からずれるという問題が生じる。一方後者
の方法は、一般に注入イオンを活性化せしめる熱処理温
度では、化合物半導体表面が化学量論的組成からずれ結
晶欠陥が発生する問題がある。
As a heat treatment method for ion-implanted compound semiconductors, silicon oxide film (S 102 >, silicon nitride film (S
A method of heat-treating the ion-implanted compound semiconductor while protecting it with a protective film such as i3N4) and a method of heat-treating it without using a protective film are used. In the former method, the ion-implanted compound semiconductor is protected with a protective film such as 3102 and subjected to heat treatment, so distortion occurs due to the difference in thermal expansion coefficient between the protective film and the compound semiconductor, resulting in crystal defects. Another problem arises in that the composition near the surface of the compound semiconductor deviates from the stoichiometric composition due to diffusion of constituent elements of the compound semiconductor into the protective film. On the other hand, the latter method generally has a problem in that the surface of the compound semiconductor deviates from the stoichiometric composition and crystal defects occur at the heat treatment temperature that activates the implanted ions.

発明の目的 本発明は上記の欠点を解決すべく新たな方法を提供する
ものであり、化合物半導体のイオン注入層の電気的特性
を向上させることを目的とする。
OBJECTS OF THE INVENTION The present invention provides a new method to solve the above-mentioned drawbacks, and aims to improve the electrical characteristics of an ion-implanted layer of a compound semiconductor.

発明の構成 イオン注入した化合物半導体の熱処理方法として、化合
物半導体を構成する元素を含む雰囲気で熱処理すること
にある。
A method of heat treating a compound semiconductor into which ions have been implanted is to perform heat treatment in an atmosphere containing elements constituting the compound semiconductor.

実施例の説明 以下本発明の実施例として磁化ガリウム(GaAs)単
結晶にn型不純物である硫黄をイオン注入した場合につ
いて述べ、本発明を詳述する。
DESCRIPTION OF EMBODIMENTS As an embodiment of the present invention, a case where sulfur, which is an n-type impurity, is ion-implanted into a magnetized gallium (GaAs) single crystal will be described below, and the present invention will be explained in detail.

クロム(Cr)  を添加した比抵抗106Ω−薗以上
の半絶縁性GaAsを真空中で700℃で3時間熱処理
し、As空孔子を形成させる。A8空孔子の形成法とし
てはガリウム雰囲気中で熱処理するとか或は結晶形成を
Ga過剰の状態で行なっても良い。このようにAs 空
格子を形成した基板に硫黄を加速電圧70KeV で1
0 ぼ 注入し、イオン注入後の熱処理をAs雰囲気中
で800℃。
Semi-insulating GaAs doped with chromium (Cr) and having a specific resistance of 106 Ω or more is heat treated at 700° C. for 3 hours in a vacuum to form As pores. As a method for forming A8 vacancies, heat treatment may be performed in a gallium atmosphere, or crystal formation may be performed in a Ga-excess state. Sulfur was added to the substrate with As vacancies formed at an accelerating voltage of 70 KeV.
The ions were implanted, and the heat treatment after the ion implantation was performed at 800°C in an As atmosphere.

30分間行った。なお、As圧は120 ff1m H
gである。へ8圧は金属As を用い、金属As を設
置した部分の温度を変えることによって種々のAs圧を
選択することが可能である。この試料の実効移動度は4
500tx /V 、5ecr一方As 圧を加えずに
Si3N4 膜を保護膜として熱処理した場合は< 1
00cm /V、secであった。なお活性化率はほと
んど変らなかった。As 雰囲気中で熱処理場合移動度
が大きくなるのは、 GaAsの′化学量論的組成から
のずれが、八8 圧を加えることで抑制されるためであ
ると推察している。
It lasted 30 minutes. In addition, As pressure is 120 ff1mH
It is g. 8 pressure uses metal As, and it is possible to select various As pressures by changing the temperature of the part where metal As is installed. The effective mobility of this sample is 4
500tx /V, 5ecr, while when heat treated with Si3N4 film as a protective film without applying As pressure, < 1
00 cm /V, sec. Note that the activation rate remained almost unchanged. It is speculated that the reason why the mobility increases when heat treated in an As atmosphere is because the deviation from the stoichiometric composition of GaAs is suppressed by applying 88 pressure.

上記説明で明らかな様に、イオン注入したG aA s
の熱処理をAs 雰囲気で行うことにより移動度が太き
くなシミ気的特性の優れた半導体装置が得られる。なお
実施例では半絶縁性GaAsを真空中で3時間熱処理し
、As空孔子を形成した後、硫黄をイオン注入したが、
この工程は必ずしも必要ではない。イオン注入量が増大
した場合、活性化率を向上させjるには有効である。
As is clear from the above explanation, the ion-implanted GaAs
By performing the heat treatment in an As atmosphere, a semiconductor device with high mobility and excellent stain resistance can be obtained. In the example, semi-insulating GaAs was heat treated in vacuum for 3 hours to form As vacancies, and then sulfur was ion-implanted.
This step is not always necessary. This is effective in increasing the activation rate when the amount of ion implantation is increased.

実施例では化合物半導体基板としてGaAgを、注入イ
オンとして硫黄について説明したが、他の化合物半導体
を用いても良いし、注入イオンについても同様である0
熱処理雰囲気として八8 雰囲気について説明したが、
化合物半動体を構成する元素からなる雰囲気であれば良
い。又イオン注入した化合物半動体と同一元素から構成
される化合物半導体に接して熱処理しても良いことは勿
論である。
In the examples, GaAg was used as the compound semiconductor substrate and sulfur was used as the implanted ions, but other compound semiconductors may be used, and the same applies to the implanted ions.
88 atmosphere was explained as a heat treatment atmosphere.
Any atmosphere may be used as long as it is composed of elements constituting a semi-dynamic compound. It goes without saying that heat treatment may be performed in contact with a compound semiconductor composed of the same element as the ion-implanted compound semi-dynamic body.

発明の効果 以上のように本発明によれば、化合物半導体のイオン注
入層の電気的特性の向上に大きく寄与するものである。
Effects of the Invention As described above, the present invention greatly contributes to improving the electrical characteristics of an ion-implanted layer of a compound semiconductor.

Claims (1)

【特許請求の範囲】[Claims] イオン注入された化合物半導体を、この化合物半導体を
構成する元素を含む雰囲気中で熱処理する工程を備えた
ことを特徴とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, comprising the step of heat-treating an ion-implanted compound semiconductor in an atmosphere containing elements constituting the compound semiconductor.
JP57184045A 1982-10-20 1982-10-20 Manufacture of semiconductor device Pending JPS58112328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57184045A JPS58112328A (en) 1982-10-20 1982-10-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57184045A JPS58112328A (en) 1982-10-20 1982-10-20 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP4384176A Division JPS6057215B2 (en) 1976-04-16 1976-04-16 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58112328A true JPS58112328A (en) 1983-07-04

Family

ID=16146394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57184045A Pending JPS58112328A (en) 1982-10-20 1982-10-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58112328A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60251631A (en) * 1984-05-28 1985-12-12 Semiconductor Res Found Manufacture of semiconductor device having non-uniform distribution of impurity concentration
JPS62163310A (en) * 1986-01-14 1987-07-20 Toshiba Corp Manufacture of compound semiconductor crystal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492511A (en) * 1972-04-20 1974-01-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492511A (en) * 1972-04-20 1974-01-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60251631A (en) * 1984-05-28 1985-12-12 Semiconductor Res Found Manufacture of semiconductor device having non-uniform distribution of impurity concentration
JPS62163310A (en) * 1986-01-14 1987-07-20 Toshiba Corp Manufacture of compound semiconductor crystal

Similar Documents

Publication Publication Date Title
JPS61201425A (en) Treatment of gaas substrate
Senzaki et al. Influences of postimplantation annealing conditions on resistance lowering in high-phosphorus-implanted 4H–SiC
JPS58112328A (en) Manufacture of semiconductor device
Tell et al. Rapid thermal annealing of elevated‐temperature silicon implants in InP
US3936321A (en) Method of making a compound semiconductor layer of high resistivity
US3445280A (en) Surface treatment of semiconductor device
JPH0797567B2 (en) Method of forming thin film
JPS6152975B2 (en)
JPS6057215B2 (en) Manufacturing method of semiconductor device
JPH012318A (en) Method of forming thin film
JPS6292327A (en) Semiconductor device and manufacture thereof
JPS6142911A (en) Forming method of conductive layer by implanting ion
JPS60211946A (en) Manufacture of semiconductor device
JPS6043658B2 (en) Manufacturing method of semiconductor device
JP3105481B2 (en) Method for doping donor impurities into silicon carbide semiconductor
JPH02239199A (en) Production of semiinsulating inp single crystal
JPH0421335B2 (en)
JPS58103122A (en) Manufacture of compound semiconductor device
JP3540918B2 (en) Method for manufacturing semiconductor device
JPS60227416A (en) Annealing method of semiconductor substrate
JPS6195515A (en) Forming of semiconductor active layer
KR100426956B1 (en) Formation method for oxidation film of SiGe epitaxial layer
JPS5927094B2 (en) Heat treatment method for compound crystals
JPH03116834A (en) Manufacture of semiconductor structure using n-type gaas
JPS61144822A (en) Formation of gaas conductive layer