JPS5797114A - Output delaying circuit - Google Patents
Output delaying circuitInfo
- Publication number
- JPS5797114A JPS5797114A JP17440480A JP17440480A JPS5797114A JP S5797114 A JPS5797114 A JP S5797114A JP 17440480 A JP17440480 A JP 17440480A JP 17440480 A JP17440480 A JP 17440480A JP S5797114 A JPS5797114 A JP S5797114A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- delivered
- time
- stopped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 abstract 3
- 230000005764 inhibitory process Effects 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P1/00—Arrangements for starting electric motors or dynamo-electric converters
- H02P1/02—Details of starting control
- H02P1/022—Security devices, e.g. correct phase sequencing
- H02P1/026—Means for delayed starting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Power Engineering (AREA)
Abstract
PURPOSE:To obtain a circuit which works assuredly even with a stop command of an instantaneous driving indication signal, by providing a circuit that delivers an inhibition signal for a certain period of time from a time point when a stop signal is delivered. CONSTITUTION:A part to be driven such as a motor 7 is driven based on a driving command signal (a), and a stop signal (b) is delivered when the signal (a) is stopped. Then the drive of the motor 7 is stopped by the signal (b) in a lapse of a certain period of time. A circuit is provided to such output circuit 3 to lead out an inhibition signal (c) for a certain period of time from a moment when the signal (b) is delivered. Thus the signal (a) to be supplied is controlled while the circuit (c) is delivered from the above-mentioned circuit. Then the part to be driven is drived in accordance with the signal (a) and when the signal (c) is stopped. For instance, a circuit shown in the diagram is used to produce both signals (b) and (c) as shown in the diagram to the intermittent signal (a). Then the motor 7 is operated by an output circuit 3 and as shown by (d) in the diagram.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17440480A JPS5797114A (en) | 1980-12-09 | 1980-12-09 | Output delaying circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17440480A JPS5797114A (en) | 1980-12-09 | 1980-12-09 | Output delaying circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5797114A true JPS5797114A (en) | 1982-06-16 |
Family
ID=15977966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17440480A Pending JPS5797114A (en) | 1980-12-09 | 1980-12-09 | Output delaying circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5797114A (en) |
-
1980
- 1980-12-09 JP JP17440480A patent/JPS5797114A/en active Pending
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