JPS5796572A - Semiconductor memory storage - Google Patents

Semiconductor memory storage

Info

Publication number
JPS5796572A
JPS5796572A JP17291480A JP17291480A JPS5796572A JP S5796572 A JPS5796572 A JP S5796572A JP 17291480 A JP17291480 A JP 17291480A JP 17291480 A JP17291480 A JP 17291480A JP S5796572 A JPS5796572 A JP S5796572A
Authority
JP
Japan
Prior art keywords
erasing
voltage
gates
data
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17291480A
Other languages
Japanese (ja)
Other versions
JPS623992B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17291480A priority Critical patent/JPS5796572A/en
Priority to DE8181305347T priority patent/DE3171836D1/en
Priority to EP81305347A priority patent/EP0053878B1/en
Priority to US06/320,935 priority patent/US4466081A/en
Publication of JPS5796572A publication Critical patent/JPS5796572A/en
Publication of JPS623992B2 publication Critical patent/JPS623992B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To eliminate the need for the supply of erasing voltage from the outside by arranging a plurality of memory cells with control gates, erasing gates and floating gates in matrix shapes and forming a means, which boosts low voltage when erasing data, to an erasing line. CONSTITUTION:An N<+> type drain 19A and an N<+> type source 19C are shaped to a P type Si substrate 11, the memory cell is formed by successively shaping the first layer conductor layer 14 functioning as the erasing gate, the second layer conductor layer 15 serving as the floating gate and the third layer conductor layer 16 functioning as the control gate through gate insulating layers, and a plurality of the memory cells are arranged in matrix shapes, thus manufacturing a programmable ROM, which electrically erases data. The voltage boosting means 51 is formed to the erasing line connected to the erasing gates, and low voltage is boosted when erasing data, thus giving the erasing line data erasing voltage. Accordingly, erasing voltage need not be afforded from the outside, and the number of pins need not also be increased.
JP17291480A 1980-12-08 1980-12-08 Semiconductor memory storage Granted JPS5796572A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP17291480A JPS5796572A (en) 1980-12-08 1980-12-08 Semiconductor memory storage
DE8181305347T DE3171836D1 (en) 1980-12-08 1981-11-11 Semiconductor memory device
EP81305347A EP0053878B1 (en) 1980-12-08 1981-11-11 Semiconductor memory device
US06/320,935 US4466081A (en) 1980-12-08 1981-11-13 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17291480A JPS5796572A (en) 1980-12-08 1980-12-08 Semiconductor memory storage

Publications (2)

Publication Number Publication Date
JPS5796572A true JPS5796572A (en) 1982-06-15
JPS623992B2 JPS623992B2 (en) 1987-01-28

Family

ID=15950680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17291480A Granted JPS5796572A (en) 1980-12-08 1980-12-08 Semiconductor memory storage

Country Status (1)

Country Link
JP (1) JPS5796572A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US5021847A (en) * 1984-05-15 1991-06-04 Waferscale Integration, Inc. Split gate memory array having staggered floating gate rows and method for making same
US7031197B2 (en) 1990-09-14 2006-04-18 Oki Electric Industry Co., Ltd. EEPROM writing and reading method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5513901A (en) * 1978-07-17 1980-01-31 Hitachi Ltd Fixed memory of semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5513901A (en) * 1978-07-17 1980-01-31 Hitachi Ltd Fixed memory of semiconductor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US5021847A (en) * 1984-05-15 1991-06-04 Waferscale Integration, Inc. Split gate memory array having staggered floating gate rows and method for making same
US7031197B2 (en) 1990-09-14 2006-04-18 Oki Electric Industry Co., Ltd. EEPROM writing and reading method

Also Published As

Publication number Publication date
JPS623992B2 (en) 1987-01-28

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