JPS5791549A - Circuit substrate structure - Google Patents

Circuit substrate structure

Info

Publication number
JPS5791549A
JPS5791549A JP55167764A JP16776480A JPS5791549A JP S5791549 A JPS5791549 A JP S5791549A JP 55167764 A JP55167764 A JP 55167764A JP 16776480 A JP16776480 A JP 16776480A JP S5791549 A JPS5791549 A JP S5791549A
Authority
JP
Japan
Prior art keywords
finger
chip
substrate
bonded
copper foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55167764A
Other languages
Japanese (ja)
Inventor
Isao Komine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP55167764A priority Critical patent/JPS5791549A/en
Publication of JPS5791549A publication Critical patent/JPS5791549A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To provide a thin mounting structure capable of largely reducing the number of steps of inspecting and correcting a circuit substrate after bonding without spending a plenty of time to be spent for setting the conditions of bonding time. CONSTITUTION:A copper foil 2 formed with a finger and a reinforcing resin substrate 6 are bonded on and under an resin substrate 5 (the material of which is polyimide coated with epoxy adhesive coating) of the side formed with the finger, are etched with the bonded copper foil to a pattern, thereby forming a finger 2a. When an IC chip 3 is bonded and sealed with resin, the substrate 5 is reduced in the size of a device hole 5a smaller than the profile size of the chip. Accordingly, the substrate 5 is interposed between the upper surface to the chip 3 and the finger 2a, thereby completely electrically insulating the space between the edge and the finger on the outer peripheral surface of the chip 3.
JP55167764A 1980-11-28 1980-11-28 Circuit substrate structure Pending JPS5791549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55167764A JPS5791549A (en) 1980-11-28 1980-11-28 Circuit substrate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55167764A JPS5791549A (en) 1980-11-28 1980-11-28 Circuit substrate structure

Publications (1)

Publication Number Publication Date
JPS5791549A true JPS5791549A (en) 1982-06-07

Family

ID=15855657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55167764A Pending JPS5791549A (en) 1980-11-28 1980-11-28 Circuit substrate structure

Country Status (1)

Country Link
JP (1) JPS5791549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224485A (en) * 1985-03-29 1986-10-06 パイオニア株式会社 Printed circuit board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224485A (en) * 1985-03-29 1986-10-06 パイオニア株式会社 Printed circuit board and manufacture thereof

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