JPS5788600A - Memory testing device - Google Patents

Memory testing device

Info

Publication number
JPS5788600A
JPS5788600A JP55164339A JP16433980A JPS5788600A JP S5788600 A JPS5788600 A JP S5788600A JP 55164339 A JP55164339 A JP 55164339A JP 16433980 A JP16433980 A JP 16433980A JP S5788600 A JPS5788600 A JP S5788600A
Authority
JP
Japan
Prior art keywords
memory
tested
controller
coincidence
coincidence signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55164339A
Other languages
Japanese (ja)
Inventor
Hideo Ishiguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55164339A priority Critical patent/JPS5788600A/en
Publication of JPS5788600A publication Critical patent/JPS5788600A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To realize the counting of the fail bit number, etc. in the real time and without causing an extreme increase of the cost, by comparing the output of a memory to be tested with the expected output information and then carrying out the control of a counter by means of a coincidence signal of the above-mentioned comparison. CONSTITUTION:A memory 11 to be tested receives the supply of the input information through a controller 12 to be tested. A comparison decider 13 compares the output of the memory 11 with the expected output information and produces a coincidence signal when a coincidence is obtained with the prescribed conditions. Thus either one of the selected auxiliary memories 14A and 14B reads the contents of storage of an address corresponding to the address within a block and stores the coincidence signal in case no past coincidence signal exists in the address to then deliver a count signal to a counter controller 16. The controller 16 receives the count signal from either one of the selected memories 14A or 14B and selects 1 unit of plural counters 17 based on the block designation information to start the counting action.
JP55164339A 1980-11-21 1980-11-21 Memory testing device Pending JPS5788600A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55164339A JPS5788600A (en) 1980-11-21 1980-11-21 Memory testing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164339A JPS5788600A (en) 1980-11-21 1980-11-21 Memory testing device

Publications (1)

Publication Number Publication Date
JPS5788600A true JPS5788600A (en) 1982-06-02

Family

ID=15791287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164339A Pending JPS5788600A (en) 1980-11-21 1980-11-21 Memory testing device

Country Status (1)

Country Link
JP (1) JPS5788600A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63127499A (en) * 1986-11-17 1988-05-31 Yamada Denon Kk Device for inspecting memory element
JPS6414797A (en) * 1987-07-08 1989-01-18 Nec Corp Semiconductor integrated memory
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63127499A (en) * 1986-11-17 1988-05-31 Yamada Denon Kk Device for inspecting memory element
JPS6414797A (en) * 1987-07-08 1989-01-18 Nec Corp Semiconductor integrated memory
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis

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