JPS55105719A - Buffer device - Google Patents
Buffer deviceInfo
- Publication number
- JPS55105719A JPS55105719A JP1336879A JP1336879A JPS55105719A JP S55105719 A JPS55105719 A JP S55105719A JP 1336879 A JP1336879 A JP 1336879A JP 1336879 A JP1336879 A JP 1336879A JP S55105719 A JPS55105719 A JP S55105719A
- Authority
- JP
- Japan
- Prior art keywords
- data
- buffer
- content
- register
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To detect the malfunction of the unit, by checking whether or not the additional information output together is according to a given information series at the output of each data, by adding the information recognizable the input order to the data inputted to the data buffer.
CONSTITUTION: The data buffer 21 has the memory unit of 16 stages, from +0W +15 in +4-bit for 1 byte for the data width. The number generators 22, 23 generate respectively equal series number, they are added by one with the address renewal numbers 11, 12, and they are constituted with the counter in 4-bit. The number information is set to the number register 24 from the generator 22, and the content is stored in the same memory location as the buffer 21 together with the content of the data register 3. Accordingly, when data is read out from the buffer 21, the number information is made together. The number information read out from the buffer 21 is set to the number register 25, the comparison circuit 26 compares the content of the register 25 with the content of the generator 23 and outputs signal when the both are not in agreement.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1336879A JPS55105719A (en) | 1979-02-09 | 1979-02-09 | Buffer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1336879A JPS55105719A (en) | 1979-02-09 | 1979-02-09 | Buffer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55105719A true JPS55105719A (en) | 1980-08-13 |
JPS5756731B2 JPS5756731B2 (en) | 1982-12-01 |
Family
ID=11831141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1336879A Granted JPS55105719A (en) | 1979-02-09 | 1979-02-09 | Buffer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55105719A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6016400U (en) * | 1983-07-07 | 1985-02-04 | 株式会社明電舎 | First-in, first-out buffer malfunction detection circuit |
JPS61208134A (en) * | 1985-03-12 | 1986-09-16 | Nec Corp | Error detection system in information processor |
JPH08221331A (en) * | 1995-02-13 | 1996-08-30 | Nec Corp | Circuit and method for detecting memory slip |
WO2007099584A1 (en) * | 2006-02-28 | 2007-09-07 | Fujitsu Limited | Error detector |
-
1979
- 1979-02-09 JP JP1336879A patent/JPS55105719A/en active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6016400U (en) * | 1983-07-07 | 1985-02-04 | 株式会社明電舎 | First-in, first-out buffer malfunction detection circuit |
JPS61208134A (en) * | 1985-03-12 | 1986-09-16 | Nec Corp | Error detection system in information processor |
JPH08221331A (en) * | 1995-02-13 | 1996-08-30 | Nec Corp | Circuit and method for detecting memory slip |
WO2007099584A1 (en) * | 2006-02-28 | 2007-09-07 | Fujitsu Limited | Error detector |
JP4834722B2 (en) * | 2006-02-28 | 2011-12-14 | 富士通株式会社 | Arithmetic processing device and control method of arithmetic processing device |
US8196028B2 (en) | 2006-02-28 | 2012-06-05 | Fujitsu Limited | Error detection device |
Also Published As
Publication number | Publication date |
---|---|
JPS5756731B2 (en) | 1982-12-01 |
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