JPS5784163A - Inspecting method for complementary mos integrated circuit - Google Patents
Inspecting method for complementary mos integrated circuitInfo
- Publication number
- JPS5784163A JPS5784163A JP55160147A JP16014780A JPS5784163A JP S5784163 A JPS5784163 A JP S5784163A JP 55160147 A JP55160147 A JP 55160147A JP 16014780 A JP16014780 A JP 16014780A JP S5784163 A JPS5784163 A JP S5784163A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- clock signal
- voltage
- input signal
- cmos integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
PURPOSE:To contrive to make failures being produced due to deterioration during operation positively detectable without performing a life test. CONSTITUTION:A CMOS integrated circuit 2 which is a reference for comparison with a CMOS integrated circuit 1 to be tested is supplied with a source voltage from a power source device 3, and an input signal is applied on it from an input signal generating circuit 4. The input signal is synchronized with a clock signal from a clock signal generating circuit 7 and is pulse which is kept to be ''1'' until the next clock signal is applied, the power source voltage is a voltage generated by a pulse voltage which is kept to be ''1'' for a short duration from the moment at which the clock signal is initiated to be superposed on a D.C. voltage, and by these signals being applied, when the CMOS integrated circuit 1 to be tested has developed a fault, a different output from an output of an integrated circuit 2 to be used as a reference is outputted, which is detected at a comparing detector circuit 5, and a judgement if it is defective or not is performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55160147A JPS5784163A (en) | 1980-11-13 | 1980-11-13 | Inspecting method for complementary mos integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55160147A JPS5784163A (en) | 1980-11-13 | 1980-11-13 | Inspecting method for complementary mos integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5784163A true JPS5784163A (en) | 1982-05-26 |
Family
ID=15708878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55160147A Pending JPS5784163A (en) | 1980-11-13 | 1980-11-13 | Inspecting method for complementary mos integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5784163A (en) |
-
1980
- 1980-11-13 JP JP55160147A patent/JPS5784163A/en active Pending
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