JPS5771159A - Heterogeneous electroplating method for circuit substrate - Google Patents
Heterogeneous electroplating method for circuit substrateInfo
- Publication number
- JPS5771159A JPS5771159A JP14630180A JP14630180A JPS5771159A JP S5771159 A JPS5771159 A JP S5771159A JP 14630180 A JP14630180 A JP 14630180A JP 14630180 A JP14630180 A JP 14630180A JP S5771159 A JPS5771159 A JP S5771159A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- device hole
- region
- circuit substrate
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 title abstract 4
- 238000009713 electroplating Methods 0.000 title 1
- 238000007747 plating Methods 0.000 abstract 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 4
- 239000011889 copper foil Substances 0.000 abstract 4
- 238000007650 screen-printing Methods 0.000 abstract 2
- 239000012790 adhesive layer Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To reduce number of processes and to improve reliability by a method wherein a film resistive against plating solution is laminated on a back surface of a flexible circuit substrate, a device hole is sealed at one side and filled with a plating resist, and a finger region of a copper foil is protected. CONSTITUTION:A copper foil 1 is laminated with an intermediary of an adhesive layer 2 on a base film 3 having a device hole 4 disposed, and by forming a finger 1a having a bonding region 1c on the copper foil 1 of the device hole, a circuit substrate is completed. A lining film 6 consisting of a film such as Luminar or the like is laminated on the back of the substrate, for example a screen printing is performed on the figer region, a plating resist 5 is filled into the device hole 4, and after applying protection on the finger, gold plating is applied on a necessary region of the copper foil 1. In this constitution by possible reduction of processes for screen printing necessary for formation of mask layers to be used for different kind of plating, a fault rate can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14630180A JPS5771159A (en) | 1980-10-21 | 1980-10-21 | Heterogeneous electroplating method for circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14630180A JPS5771159A (en) | 1980-10-21 | 1980-10-21 | Heterogeneous electroplating method for circuit substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5771159A true JPS5771159A (en) | 1982-05-01 |
JPS6252947B2 JPS6252947B2 (en) | 1987-11-07 |
Family
ID=15404578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14630180A Granted JPS5771159A (en) | 1980-10-21 | 1980-10-21 | Heterogeneous electroplating method for circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5771159A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0107071A2 (en) * | 1982-09-27 | 1984-05-02 | Siemens Aktiengesellschaft | Method of manufacturing semiconductor chip film carriers |
JPS63500837A (en) * | 1985-08-08 | 1988-03-24 | マツクダ−ミツド インコ−ポレ−テツド | Printed circuit board manufacturing method |
-
1980
- 1980-10-21 JP JP14630180A patent/JPS5771159A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0107071A2 (en) * | 1982-09-27 | 1984-05-02 | Siemens Aktiengesellschaft | Method of manufacturing semiconductor chip film carriers |
JPS63500837A (en) * | 1985-08-08 | 1988-03-24 | マツクダ−ミツド インコ−ポレ−テツド | Printed circuit board manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
JPS6252947B2 (en) | 1987-11-07 |
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