JPS5771159A - Heterogeneous electroplating method for circuit substrate - Google Patents

Heterogeneous electroplating method for circuit substrate

Info

Publication number
JPS5771159A
JPS5771159A JP14630180A JP14630180A JPS5771159A JP S5771159 A JPS5771159 A JP S5771159A JP 14630180 A JP14630180 A JP 14630180A JP 14630180 A JP14630180 A JP 14630180A JP S5771159 A JPS5771159 A JP S5771159A
Authority
JP
Japan
Prior art keywords
copper foil
device hole
region
circuit substrate
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14630180A
Other languages
Japanese (ja)
Other versions
JPS6252947B2 (en
Inventor
Yoshihiro Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP14630180A priority Critical patent/JPS5771159A/en
Publication of JPS5771159A publication Critical patent/JPS5771159A/en
Publication of JPS6252947B2 publication Critical patent/JPS6252947B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce number of processes and to improve reliability by a method wherein a film resistive against plating solution is laminated on a back surface of a flexible circuit substrate, a device hole is sealed at one side and filled with a plating resist, and a finger region of a copper foil is protected. CONSTITUTION:A copper foil 1 is laminated with an intermediary of an adhesive layer 2 on a base film 3 having a device hole 4 disposed, and by forming a finger 1a having a bonding region 1c on the copper foil 1 of the device hole, a circuit substrate is completed. A lining film 6 consisting of a film such as Luminar or the like is laminated on the back of the substrate, for example a screen printing is performed on the figer region, a plating resist 5 is filled into the device hole 4, and after applying protection on the finger, gold plating is applied on a necessary region of the copper foil 1. In this constitution by possible reduction of processes for screen printing necessary for formation of mask layers to be used for different kind of plating, a fault rate can be reduced.
JP14630180A 1980-10-21 1980-10-21 Heterogeneous electroplating method for circuit substrate Granted JPS5771159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14630180A JPS5771159A (en) 1980-10-21 1980-10-21 Heterogeneous electroplating method for circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14630180A JPS5771159A (en) 1980-10-21 1980-10-21 Heterogeneous electroplating method for circuit substrate

Publications (2)

Publication Number Publication Date
JPS5771159A true JPS5771159A (en) 1982-05-01
JPS6252947B2 JPS6252947B2 (en) 1987-11-07

Family

ID=15404578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14630180A Granted JPS5771159A (en) 1980-10-21 1980-10-21 Heterogeneous electroplating method for circuit substrate

Country Status (1)

Country Link
JP (1) JPS5771159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0107071A2 (en) * 1982-09-27 1984-05-02 Siemens Aktiengesellschaft Method of manufacturing semiconductor chip film carriers
JPS63500837A (en) * 1985-08-08 1988-03-24 マツクダ−ミツド　インコ−ポレ−テツド Printed circuit board manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0107071A2 (en) * 1982-09-27 1984-05-02 Siemens Aktiengesellschaft Method of manufacturing semiconductor chip film carriers
JPS63500837A (en) * 1985-08-08 1988-03-24 マツクダ−ミツド　インコ−ポレ−テツド Printed circuit board manufacturing method

Also Published As

Publication number Publication date
JPS6252947B2 (en) 1987-11-07

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