JPS5769761A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5769761A JPS5769761A JP55144309A JP14430980A JPS5769761A JP S5769761 A JPS5769761 A JP S5769761A JP 55144309 A JP55144309 A JP 55144309A JP 14430980 A JP14430980 A JP 14430980A JP S5769761 A JPS5769761 A JP S5769761A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- film
- resist
- spacer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
PURPOSE:To eliminate the crack at a passivation film in a semiconductor device by reducing the size of a hole of a spacer resist for lifting off smaller than the size of a hole of the passivation film. CONSTITUTION:An aluminum wire 2 is formed on a wafer 1 completed at the diffusing and oxidizing steps, etc, and a passivation film (PV film) 3 is formed thereon. The side of the hole 4a of a spacer resist 4 for lifting off is formed smaller than that of the hole 3a of the PV film 3 in such a manner that a various metal 5 is not accumulated directly on the film 3 over the entire surface. A part of the spacer resist 4 interposed between the hole of the plated resist 6 and the hole 4a of the spacer resist is not exfolidated but is remained, and the aluminum pad 2 in the vicinity of the hole 3a of the film 3 is external shielded. In this manner, it can eliminate the crack at the PV film and the introduction of water thereto and the corrosion thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55144309A JPS5769761A (en) | 1980-10-17 | 1980-10-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55144309A JPS5769761A (en) | 1980-10-17 | 1980-10-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5769761A true JPS5769761A (en) | 1982-04-28 |
Family
ID=15359081
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55144309A Pending JPS5769761A (en) | 1980-10-17 | 1980-10-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5769761A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59104144A (en) * | 1982-12-07 | 1984-06-15 | Citizen Watch Co Ltd | Forming method for salient electrode |
EP0657923A2 (en) * | 1993-12-10 | 1995-06-14 | International Business Machines Corporation | Method of protecting a solder ball during an etch process, by applying a resist around the base of the solder ball |
CN103632985A (en) * | 2012-08-21 | 2014-03-12 | 英飞凌科技股份有限公司 | Method for manufacturing a metal pad structure of a die, a die arrangement and a chip arrangement |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52155056A (en) * | 1976-06-18 | 1977-12-23 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
-
1980
- 1980-10-17 JP JP55144309A patent/JPS5769761A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52155056A (en) * | 1976-06-18 | 1977-12-23 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59104144A (en) * | 1982-12-07 | 1984-06-15 | Citizen Watch Co Ltd | Forming method for salient electrode |
EP0657923A2 (en) * | 1993-12-10 | 1995-06-14 | International Business Machines Corporation | Method of protecting a solder ball during an etch process, by applying a resist around the base of the solder ball |
EP0657923A3 (en) * | 1993-12-10 | 1996-06-12 | Ibm | Method of protecting a solder ball during an etch process, by applying a resist around the base of the solder ball. |
CN103632985A (en) * | 2012-08-21 | 2014-03-12 | 英飞凌科技股份有限公司 | Method for manufacturing a metal pad structure of a die, a die arrangement and a chip arrangement |
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