JPS576954A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS576954A
JPS576954A JP8003280A JP8003280A JPS576954A JP S576954 A JPS576954 A JP S576954A JP 8003280 A JP8003280 A JP 8003280A JP 8003280 A JP8003280 A JP 8003280A JP S576954 A JPS576954 A JP S576954A
Authority
JP
Japan
Prior art keywords
processor bus
memory
multiprocessor system
processor
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8003280A
Other languages
Japanese (ja)
Other versions
JPS6119055B2 (en
Inventor
Akira Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8003280A priority Critical patent/JPS576954A/en
Publication of JPS576954A publication Critical patent/JPS576954A/en
Publication of JPS6119055B2 publication Critical patent/JPS6119055B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To enhance the working efficiency of a multiprocessor system, by providing a processor bus selecting means to each of plural data transfer memories in the multiprocessor system. CONSTITUTION:The processor bus of the #1 system when a processor bus selecting flip-flop 132 is 1. In other words, a read signal MR1 or a write signal MW1 of the #1 system, a decoder 123, a 3-state circuit 127 and a two-way driver 129 are selected and driven. Thus a reading or writing of the data becomes possible to the processor bus of the #1 system from a memory 133 and from the processor bus of the #1 system to the memory 133 respectively. On the other hand, the processor bus of the #2 system is selected when the flip-flop 132 is 0. Such memory cotrol circuit is provided to each memory to realize an independent and simultaneous transfer of data between each memory and processor bus. As a result, the queuing time is eliminated for each processor to enhance the working efficiency of a multiprocessor system.
JP8003280A 1980-06-13 1980-06-13 Multiprocessor system Granted JPS576954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8003280A JPS576954A (en) 1980-06-13 1980-06-13 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8003280A JPS576954A (en) 1980-06-13 1980-06-13 Multiprocessor system

Publications (2)

Publication Number Publication Date
JPS576954A true JPS576954A (en) 1982-01-13
JPS6119055B2 JPS6119055B2 (en) 1986-05-15

Family

ID=13706918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8003280A Granted JPS576954A (en) 1980-06-13 1980-06-13 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS576954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149262A (en) * 1984-08-16 1986-03-11 Oki Electric Ind Co Ltd Page memory information transfer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149262A (en) * 1984-08-16 1986-03-11 Oki Electric Ind Co Ltd Page memory information transfer system

Also Published As

Publication number Publication date
JPS6119055B2 (en) 1986-05-15

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