JPS5768943A - Bipolar pulse error discrimination circuit - Google Patents

Bipolar pulse error discrimination circuit

Info

Publication number
JPS5768943A
JPS5768943A JP14370380A JP14370380A JPS5768943A JP S5768943 A JPS5768943 A JP S5768943A JP 14370380 A JP14370380 A JP 14370380A JP 14370380 A JP14370380 A JP 14370380A JP S5768943 A JPS5768943 A JP S5768943A
Authority
JP
Japan
Prior art keywords
circuit
pulse
signal
outputted
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14370380A
Other languages
Japanese (ja)
Inventor
Masanori Arai
Koji Nishizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14370380A priority Critical patent/JPS5768943A/en
Publication of JPS5768943A publication Critical patent/JPS5768943A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To detect surely dipolar pulse code error, by constituting the circuit with the 2nd pulse detection circuit of two consecutive same polarity pulse of a bipolar pulse, circuit converting the bipolar pulse into monopolar pulse and dividing frequency, storage circuit for the output of the frequency division circuit, and circuit detecting the changing point of the storage circuit. CONSTITUTION:An HDB-3 code (a) added with a bipolar violation mark is inputted to a rectifying circuit 1, the positive polarity pulse (b) and the negative polarity pulse (c) are detected and inputted to a detection circuit 2 and a frequency division circuit 3. The 2nd pulse of the two same polarity pulses consecutive in the circuit 2 is detected, and an output signal (e) is applied to a clock input (c) of an FF51 of a storage circuit 5. In the circuit 2, a frequency division signal (f) is outputted from the signals (b), (c), and this delayed 4 signal (f)' is applied to a data input D of the circuit 5. If no error in the code (a) in the circuit 5, a high level signal (g) is outputted to a changing point detection circuit 6 and a low level signal (h) is outputted from the circuit 6, but if any error is in the code (a), the signal (g) changes to a low level and the high level error detection signal (h) is outputted from the circuit 6.
JP14370380A 1980-10-16 1980-10-16 Bipolar pulse error discrimination circuit Pending JPS5768943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14370380A JPS5768943A (en) 1980-10-16 1980-10-16 Bipolar pulse error discrimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14370380A JPS5768943A (en) 1980-10-16 1980-10-16 Bipolar pulse error discrimination circuit

Publications (1)

Publication Number Publication Date
JPS5768943A true JPS5768943A (en) 1982-04-27

Family

ID=15345001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14370380A Pending JPS5768943A (en) 1980-10-16 1980-10-16 Bipolar pulse error discrimination circuit

Country Status (1)

Country Link
JP (1) JPS5768943A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4658399A (en) * 1983-12-20 1987-04-14 Italtel Societa Italiana Telecomunicazioni Spa Circuit arrangement designed to pick up the error rate in numerical transmission systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4658399A (en) * 1983-12-20 1987-04-14 Italtel Societa Italiana Telecomunicazioni Spa Circuit arrangement designed to pick up the error rate in numerical transmission systems

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