JPS5766518A - Bit clock circuit of pcm processor - Google Patents

Abstract

PURPOSE:To obtain a bit clock synchronizing with data containing jitters, by detecting and inputting the edge of each data of a clock generator and a PCM signal to a frequency divider which divides the frequency of a clock signal. CONSTITUTION:In a clock generator 14 a clock pulse is obtained by increasing a bit clock in recording by an integer N, on the basis of a horizontal synchronizing signal obtained from a synchronous separating circuit 12, and the clock pulse is inputted to a frequency divider 16. An edge detecting circuit 15 outputs pulse N1- N14- corresponding to negative edges of data a1-a14-, and they are outputted through the frequency divider 16. The frequency of the output signal is equal to that of the bit clock in recording and it is cleared at each negative edge of the data, so it synchronizes with the data containing jitters. Therefore, the output of the frequency divider 16 is inputted to a latch circuit 13 to be latched accurately. Thus, the bit clock synchronizing with the data containing the jitters is obtained.