JPS5763936A - Phase-locked loop - Google Patents
Phase-locked loopInfo
- Publication number
- JPS5763936A JPS5763936A JP55139368A JP13936880A JPS5763936A JP S5763936 A JPS5763936 A JP S5763936A JP 55139368 A JP55139368 A JP 55139368A JP 13936880 A JP13936880 A JP 13936880A JP S5763936 A JPS5763936 A JP S5763936A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- voltage
- pll
- vco10
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000035945 sensitivity Effects 0.000 abstract 2
- 230000010355 oscillation Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To obtain a wide PLL frequency range with detuning reduced, by controlling a voltage-controlled oscillator VCO by a voltage regarding an output frequency setting digital data supplied to a programmable frequency divider. CONSTITUTION:A digital frequency-division indication signal P supplied to a programmable frequency divider 12 is supplied to a D/A converter 22 as well. The output Vo of the converter 22 has a voltage value corresponding to the specified frequency-division ratio N of the frequency divider 12, and a VCO10 is controlled by the voltage. The VCO10 has an oscillation frequency specified by the Vo, and the frequency is divided by N at the frequency divider 12, whose output is compared, in terms of phase, with a reference signal from a reference frequency generator 14 by a phase comparator 16 to supply their difference to the VCO10 as a voltage Vp through an LPF18. The principal decision on a PLL output frequency by the signal P is made by the output Vo of the converter 22 and only the correction for accurate PLL output setting is performed by the output Vp of the LPF18, so the modulation sensitivity of VCO is set small, thereby reducing noises in the PLL output signal following up large modulation sensitivity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55139368A JPS5763936A (en) | 1980-10-07 | 1980-10-07 | Phase-locked loop |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55139368A JPS5763936A (en) | 1980-10-07 | 1980-10-07 | Phase-locked loop |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5763936A true JPS5763936A (en) | 1982-04-17 |
Family
ID=15243692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55139368A Pending JPS5763936A (en) | 1980-10-07 | 1980-10-07 | Phase-locked loop |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5763936A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4568888A (en) * | 1983-11-08 | 1986-02-04 | Trw Inc. | PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction |
US5281927A (en) * | 1993-05-20 | 1994-01-25 | Codex Corp. | Circuit and method of controlling a VCO with capacitive loads |
-
1980
- 1980-10-07 JP JP55139368A patent/JPS5763936A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4568888A (en) * | 1983-11-08 | 1986-02-04 | Trw Inc. | PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction |
US5281927A (en) * | 1993-05-20 | 1994-01-25 | Codex Corp. | Circuit and method of controlling a VCO with capacitive loads |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4673892A (en) | Phase locked loop frequency synthesizer with battery saving circuit | |
US4446446A (en) | Programmable frequency synthesizer primarily for use in an atomic clock | |
JPS6448267A (en) | Pll circuit for magnetic disk device | |
ATE77519T1 (en) | IN PHASE LOCKED DIGITAL SYNTHETIC. | |
CA2010265A1 (en) | Phase-locked loop apparatus | |
CA2071421A1 (en) | Automatic frequency control circuit | |
US6031426A (en) | Phase locked loop with digital vernier control | |
JPS5763936A (en) | Phase-locked loop | |
EP0206247A3 (en) | Pll frequency synthesizer | |
JPS5486256A (en) | Frequency control circuit | |
US4642574A (en) | Digital quartz-stabilized FM discriminator | |
JPS5745730A (en) | Phase-locked loop circuit | |
JPS5776930A (en) | Frequency shift signal generating system using pll | |
JPS5694841A (en) | Pilot signal production system | |
DK224688D0 (en) | OSCILLATOR EQUIPMENT TO PROVIDE AT LEAST TWO DIFFERENT FREQUENCIES | |
JPS5466757A (en) | Pll system | |
JPS54122914A (en) | Radio receiver of pll frequency synthesizer system | |
JPS5732133A (en) | Phase-synchronous oscillator | |
JPS6178225A (en) | Automatic frequency controller | |
JPS5714221A (en) | Phase-synchronous oscillating circuit | |
JPS63281518A (en) | Phase locked loop device | |
JPS6429174A (en) | Clock generation circuit | |
JPS5754437A (en) | Pll system intermittent operation | |
Wang et al. | VCO FQR millimeter-wave phase-locked sources | |
JPS56169435A (en) | Phase synchronization oscillator |