JPS5761356A - Information transmission and reception device - Google Patents
Information transmission and reception deviceInfo
- Publication number
- JPS5761356A JPS5761356A JP13892580A JP13892580A JPS5761356A JP S5761356 A JPS5761356 A JP S5761356A JP 13892580 A JP13892580 A JP 13892580A JP 13892580 A JP13892580 A JP 13892580A JP S5761356 A JPS5761356 A JP S5761356A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- terminal
- added
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Alarm Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To confirm on the transmittor side the fact that information is received on the receiver, by outputting on-signal of a switch from the 1st terminal and by operating an alarm device in correspondence to a signal inputted from the 2nd terminal. CONSTITUTION:A push-button switch S is turned on and the output of a flip flop FF is set to high level. As a result, a pulse signal which is input from a terminal P is added to a counter CT through an AND gate AN1 and counted. The output of the 1st and 3rd bits of the counter CT is added to an AND gate AN4 through an AND gate AN3. While, high-level voltage output from a terminal 1a is added to the AND gate AN4 if a transmission line III and a feedback line V are normal. As a result, a pulse having a constant pulse width is outputted from the AND gate AN4 and light emitting diode illuminates for a constant time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13892580A JPS5761356A (en) | 1980-09-30 | 1980-09-30 | Information transmission and reception device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13892580A JPS5761356A (en) | 1980-09-30 | 1980-09-30 | Information transmission and reception device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5761356A true JPS5761356A (en) | 1982-04-13 |
Family
ID=15233332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13892580A Pending JPS5761356A (en) | 1980-09-30 | 1980-09-30 | Information transmission and reception device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5761356A (en) |
-
1980
- 1980-09-30 JP JP13892580A patent/JPS5761356A/en active Pending
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