JPS5750429A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5750429A
JPS5750429A JP12669480A JP12669480A JPS5750429A JP S5750429 A JPS5750429 A JP S5750429A JP 12669480 A JP12669480 A JP 12669480A JP 12669480 A JP12669480 A JP 12669480A JP S5750429 A JPS5750429 A JP S5750429A
Authority
JP
Japan
Prior art keywords
layer
photo
platinum
metal
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12669480A
Other languages
Japanese (ja)
Inventor
Tsutomu Akashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12669480A priority Critical patent/JPS5750429A/en
Publication of JPS5750429A publication Critical patent/JPS5750429A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To enable patterning through etching without reforming a photo-resist by using an upper layer metal as an etching resisting mask for a lower layer metal. CONSTITUTION:A P type base resion 2, an N type emitter region 3 and an N type collector contact region 4 are formed to an N type silicon wafer 1, the surface of the wafer is coated with an insulating film 5, and windows for contact are shaped. Platinum is evaporated and thermally treated and a platinum silicide 9 is formed, and platinum on the insulating film 5 is removed. A W (tungsten) layer 10 as a diffusion barrier metal and an Al layer 11 as a wiring metal are shaped. The Al layer is dry-etched using the photo-resists 12 as masks while the photo-resists 12 are also removed. W is etched employing Al as masks while using an etching agent (such as CF4 gas) which etches W but does not etch Al.
JP12669480A 1980-09-12 1980-09-12 Manufacture of semiconductor device Pending JPS5750429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12669480A JPS5750429A (en) 1980-09-12 1980-09-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12669480A JPS5750429A (en) 1980-09-12 1980-09-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5750429A true JPS5750429A (en) 1982-03-24

Family

ID=14941528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12669480A Pending JPS5750429A (en) 1980-09-12 1980-09-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5750429A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151889U (en) * 1982-04-07 1983-10-12 株式会社精工舎 display device
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4612257A (en) * 1983-05-02 1986-09-16 Signetics Corporation Electrical interconnection for semiconductor integrated circuits
DE3711657A1 (en) * 1986-04-07 1987-10-15 Hitachi Ltd GENERATOR / MOTOR DEVICE WITH VARIABLE SPEED
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US6111319A (en) * 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53135267A (en) * 1977-04-30 1978-11-25 Matsushita Electric Ind Co Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53135267A (en) * 1977-04-30 1978-11-25 Matsushita Electric Ind Co Ltd Production of semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151889U (en) * 1982-04-07 1983-10-12 株式会社精工舎 display device
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4612257A (en) * 1983-05-02 1986-09-16 Signetics Corporation Electrical interconnection for semiconductor integrated circuits
DE3711657A1 (en) * 1986-04-07 1987-10-15 Hitachi Ltd GENERATOR / MOTOR DEVICE WITH VARIABLE SPEED
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
US5371410A (en) * 1991-03-27 1994-12-06 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US6033980A (en) * 1995-12-19 2000-03-07 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US6111319A (en) * 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US6180517B1 (en) 1995-12-19 2001-01-30 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit

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