JPS5750398A - Error checking system - Google Patents

Error checking system

Info

Publication number
JPS5750398A
JPS5750398A JP55125157A JP12515780A JPS5750398A JP S5750398 A JPS5750398 A JP S5750398A JP 55125157 A JP55125157 A JP 55125157A JP 12515780 A JP12515780 A JP 12515780A JP S5750398 A JPS5750398 A JP S5750398A
Authority
JP
Japan
Prior art keywords
circuit
error
supplied
signal
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55125157A
Other languages
Japanese (ja)
Inventor
Kazuhiro Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55125157A priority Critical patent/JPS5750398A/en
Publication of JPS5750398A publication Critical patent/JPS5750398A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To facilitate the decision for a soft or hard error in the data reading mode, by storing the detection of error for the readout data and then reading out again the same address by the detection of error to perform the detection of error. CONSTITUTION:Both a memory 1 and a sequence controller 2 are controlled by the timing signal supplied from a generating circuit 3. The data read out from a memory 1 is supplied to an ECC circuit 4 to perform the detection and correction of a 1-bit error. Then an error detection signal ED is supplied to the circuit 3. The circuit 3 writes again the data corrected through the circuit 4 into the same address of the memory 1. After this, the circuit 3 reads out again the data of the same address out of the memory 1 and then supplies it to the circuit 4. Both an error signal ER and clock signal CL supplied from the circuit 4 are supplied to a deciding circuit 5. The circuit 5 delivers a signal HE for a hard error and a signal SE for a soft error, respectively.
JP55125157A 1980-09-09 1980-09-09 Error checking system Pending JPS5750398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55125157A JPS5750398A (en) 1980-09-09 1980-09-09 Error checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55125157A JPS5750398A (en) 1980-09-09 1980-09-09 Error checking system

Publications (1)

Publication Number Publication Date
JPS5750398A true JPS5750398A (en) 1982-03-24

Family

ID=14903280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55125157A Pending JPS5750398A (en) 1980-09-09 1980-09-09 Error checking system

Country Status (1)

Country Link
JP (1) JPS5750398A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006146920A (en) * 2004-11-17 2006-06-08 Sun Microsyst Inc Method and apparatus for classifying memory error

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006146920A (en) * 2004-11-17 2006-06-08 Sun Microsyst Inc Method and apparatus for classifying memory error

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