JPS5748841A - Clock selection system - Google Patents

Clock selection system

Info

Publication number
JPS5748841A
JPS5748841A JP55123428A JP12342880A JPS5748841A JP S5748841 A JPS5748841 A JP S5748841A JP 55123428 A JP55123428 A JP 55123428A JP 12342880 A JP12342880 A JP 12342880A JP S5748841 A JPS5748841 A JP S5748841A
Authority
JP
Japan
Prior art keywords
data signal
clock signal
rise
fall
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55123428A
Other languages
Japanese (ja)
Other versions
JPS5949745B2 (en
Inventor
Michinobu Ohata
Masanori Kajiwara
Takahiro Furukawa
Koji Mizushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55123428A priority Critical patent/JPS5949745B2/en
Publication of JPS5748841A publication Critical patent/JPS5748841A/en
Publication of JPS5949745B2 publication Critical patent/JPS5949745B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To decrease the probability of data read-in error production by sampling the data signal at the rise and fall of a clock signal, in a system sampling in the same frequency as that of the data signal. CONSTITUTION:In a receiver for a digital communication, the discrimination as to if the fall changing point and rise changing point of a clock signal S4 are superimposed on an uncertain area of a data signal S1 or not, is performed at phase comparators 3, 4. If the changing point of the clock signal S4 is superimposed on the uncertain area of the data signal S1, the data signal S1 is sampled with the fall or rise of the clock signal S4. Thus, the sampling of the uncertain area of the data signal S1 is avoided, allowing to decrease the probability of data read-in error production.
JP55123428A 1980-09-08 1980-09-08 Clock selection method Expired JPS5949745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55123428A JPS5949745B2 (en) 1980-09-08 1980-09-08 Clock selection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55123428A JPS5949745B2 (en) 1980-09-08 1980-09-08 Clock selection method

Publications (2)

Publication Number Publication Date
JPS5748841A true JPS5748841A (en) 1982-03-20
JPS5949745B2 JPS5949745B2 (en) 1984-12-04

Family

ID=14860315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55123428A Expired JPS5949745B2 (en) 1980-09-08 1980-09-08 Clock selection method

Country Status (1)

Country Link
JP (1) JPS5949745B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2569070A1 (en) * 1984-08-10 1986-02-14 Milon Jean METHOD AND DEVICE FOR QUICKLY ACQUIRING THE RHYTHM AND PHASE OF A DIGITAL SIGNAL
US5126587A (en) * 1990-03-26 1992-06-30 Siemens Aktiengesellschaft Synchronization circuit configuration
JPH05130089A (en) * 1991-10-31 1993-05-25 Omron Corp Data transmitter
DE102007019826B4 (en) * 2006-04-26 2010-11-11 Realtek Semiconductor Corp. Phase selector for data transmission device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2569070A1 (en) * 1984-08-10 1986-02-14 Milon Jean METHOD AND DEVICE FOR QUICKLY ACQUIRING THE RHYTHM AND PHASE OF A DIGITAL SIGNAL
US5126587A (en) * 1990-03-26 1992-06-30 Siemens Aktiengesellschaft Synchronization circuit configuration
JPH05130089A (en) * 1991-10-31 1993-05-25 Omron Corp Data transmitter
DE102007019826B4 (en) * 2006-04-26 2010-11-11 Realtek Semiconductor Corp. Phase selector for data transmission device
US7936857B2 (en) 2006-04-26 2011-05-03 Realtek Semiconductor Corp. Phase selector for data transmitting device

Also Published As

Publication number Publication date
JPS5949745B2 (en) 1984-12-04

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