JPS5745659A - Memory address managing device - Google Patents
Memory address managing deviceInfo
- Publication number
- JPS5745659A JPS5745659A JP55121077A JP12107780A JPS5745659A JP S5745659 A JPS5745659 A JP S5745659A JP 55121077 A JP55121077 A JP 55121077A JP 12107780 A JP12107780 A JP 12107780A JP S5745659 A JPS5745659 A JP S5745659A
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- main storage
- storage device
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
Abstract
PURPOSE:To use the same address duplicatedly in a main storage device and an input/output device, by providing a flip-flop which can discriminate the access of processor either of a main storage device or an input/output device. CONSTITUTION:An address signal 6 of a common bus CB and the content of a switch register 7 where the address range of an input/output device is preset, are connected to inputs A and B of a comparator 8, and on the other hand, the AND output of an AND circuit 13 between the decoder 14 and a memory start signal 11 and one bit of a data signal 16 set or reset a flip-flop 15, and the Q output of the flip-flop 15 and the A>=B output of the said comparator 8 for the AND output of an AND circuit 13 is obtained on a common bus as a pause signal 10 which stops the main storage device. Thus, according to the presence or absence of the pause signal, the input/output device and the main storage device select and use the address automatically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55121077A JPS5745659A (en) | 1980-09-03 | 1980-09-03 | Memory address managing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55121077A JPS5745659A (en) | 1980-09-03 | 1980-09-03 | Memory address managing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5745659A true JPS5745659A (en) | 1982-03-15 |
Family
ID=14802274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55121077A Pending JPS5745659A (en) | 1980-09-03 | 1980-09-03 | Memory address managing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5745659A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61107049U (en) * | 1984-12-15 | 1986-07-07 | ||
JPS62174843A (en) * | 1986-01-29 | 1987-07-31 | Hitachi Ltd | Switching system for memory priority |
-
1980
- 1980-09-03 JP JP55121077A patent/JPS5745659A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61107049U (en) * | 1984-12-15 | 1986-07-07 | ||
JPS62174843A (en) * | 1986-01-29 | 1987-07-31 | Hitachi Ltd | Switching system for memory priority |
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