JPS5742165A - Manufacture of mis type field effect transistor device - Google Patents

Abstract

PURPOSE:To make the surface of elements flat while elevating the integration level by forming an MIS type FET by ion implantation using a polycrystalline Si layer in the manufacture of the MIS type FET. CONSTITUTION:An thick insulation layer 34 for isolating elements is formed which making flat the surface of the perimeter of a p type semiconductor substrate 31 and then, a thin insulation layer 55 is applied on an island-shaped region 33 surrounded thereby to be a gate insulation layer. Then, a polycrystalline layer 56 containing an n type impurity is grown on the entire surface, heat treated only on the surface thereof to be changed to an SiO2 layer 57 and again, a polycrystalline Si layer 58 is stacked over the entire surface. Thereafter, masks 60 and 60a of a specified pattern are provided and the exposed section of the layer 58 is removed by etching. With the removal of the masks 60 and 60a, only the surface and the side of the layers 58 and 58a exposed are changed to SiO2 layers 63, 63a, 63b and 63c respectively, which are used as masks and ion is implanted to form ion implanted regions 64 and 65 on the interface between the substrate 31 and the layer 56. The impurity is diffused in the substrate 31 by heat treatment to form an n type source region 38 and a drain region 39.