JPS6430270A - Manufacture of insulated-gate semiconductor device - Google Patents

Manufacture of insulated-gate semiconductor device

Info

Publication number
JPS6430270A
JPS6430270A JP18639687A JP18639687A JPS6430270A JP S6430270 A JPS6430270 A JP S6430270A JP 18639687 A JP18639687 A JP 18639687A JP 18639687 A JP18639687 A JP 18639687A JP S6430270 A JPS6430270 A JP S6430270A
Authority
JP
Japan
Prior art keywords
film
trench
rie
sidewalls
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18639687A
Other languages
Japanese (ja)
Inventor
Tetsuo Izawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18639687A priority Critical patent/JPS6430270A/en
Publication of JPS6430270A publication Critical patent/JPS6430270A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To achieve a good controllability by a method wherein sidewalls containing impurity of the conductivity type opposite to the conductivity type of a semiconductor layer are formed in a trench and the impurity in the sidewalls is directly introduced into the semiconductor layer through the region from which the sidewalls are removed to form low impurity concentration layers. CONSTITUTION:A silicon oxide film 21 and a silicon nitride film 22 are formed on the surface of a semiconductor substrate 20 in this order and a trench 23 is formed. Then a silicon nitride film 24 is further formed in the trench 23 and on the surface of the film 22 and the silicon nitride films 24a are left on the side surfaces of the trench 23 by RIE. Then a PSG film 25 is formed and the PSG films 25a are left on the side surfaces of the trench 23a by RIE. If, then, annealing is carried out by RTA, low impurity concentration layer 26 are formed. Then the films 25a and 24a are removed and a gate oxide film 27 is formed and, after a polycrystalline silicon film 28 is deposited, the polycrystalline silicon film 28a is left by RIE. Then, the film 21 is etched off and a source electrode 291 and a drain electrode 292 are formed by using the film (gate electrode) 28a as a mask.
JP18639687A 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device Pending JPS6430270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18639687A JPS6430270A (en) 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18639687A JPS6430270A (en) 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device

Publications (1)

Publication Number Publication Date
JPS6430270A true JPS6430270A (en) 1989-02-01

Family

ID=16187668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18639687A Pending JPS6430270A (en) 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device

Country Status (1)

Country Link
JP (1) JPS6430270A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02231729A (en) * 1989-03-03 1990-09-13 Nec Corp Manufacture of semiconductor device
JPH07211382A (en) * 1993-12-21 1995-08-11 Molex Inc Electric connector
EP0777269A2 (en) * 1995-12-01 1997-06-04 Sharp Kabushiki Kaisha MOS transistor and fabrication process therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02231729A (en) * 1989-03-03 1990-09-13 Nec Corp Manufacture of semiconductor device
JPH07211382A (en) * 1993-12-21 1995-08-11 Molex Inc Electric connector
EP0777269A2 (en) * 1995-12-01 1997-06-04 Sharp Kabushiki Kaisha MOS transistor and fabrication process therefor
EP0777269A3 (en) * 1995-12-01 1999-02-03 Sharp Kabushiki Kaisha MOS transistor and fabrication process therefor

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