JPS5734350A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5734350A
JPS5734350A JP11050180A JP11050180A JPS5734350A JP S5734350 A JPS5734350 A JP S5734350A JP 11050180 A JP11050180 A JP 11050180A JP 11050180 A JP11050180 A JP 11050180A JP S5734350 A JPS5734350 A JP S5734350A
Authority
JP
Japan
Prior art keywords
cover
frame
chip
grooves
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11050180A
Other languages
Japanese (ja)
Inventor
Shogo Ariyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11050180A priority Critical patent/JPS5734350A/en
Publication of JPS5734350A publication Critical patent/JPS5734350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase the adhesive strength of a case and cover as well as to improve the workability for the subject semiconductor by a method wherein grooves are provided at the section opposing to the inner wall of the opening part of the case, in the recess section of which a chip is stored, and a rectangular cover is fitted by sliding along the grooves. CONSTITUTION:A ceramic substrate 3 is soldered on the heat sink 4 fixed at one of the openings on a frame 11, the chip 1 is soldered at the conductor 2 on the substrate 3 and, at the same time, an electrode is connected to lead-out terminals 6a- 6c. After resin material 8 is filled in the case wherein the chip 1 is contained, the cover 12 is fitted to the grooves 11a and 11b provided at the other opening part of the frame 11 and then the cover 12 and the frame 11 are adhered and hermetically sealed using an adhesive material. Through these procedures, the usage of a special jig is unnecessitated when performing a heat treatment on the bonded frame and the cover, the workability is improved and the lowering of the adhesive strength can also be prevented.
JP11050180A 1980-08-09 1980-08-09 Semiconductor device Pending JPS5734350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11050180A JPS5734350A (en) 1980-08-09 1980-08-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11050180A JPS5734350A (en) 1980-08-09 1980-08-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5734350A true JPS5734350A (en) 1982-02-24

Family

ID=14537358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11050180A Pending JPS5734350A (en) 1980-08-09 1980-08-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5734350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4664675B2 (en) * 2002-09-02 2011-04-06 キネティック リミテッド Hermetically sealed
JP2019169669A (en) * 2018-03-26 2019-10-03 キヤノン株式会社 Electronic module and imaging system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4664675B2 (en) * 2002-09-02 2011-04-06 キネティック リミテッド Hermetically sealed
JP2019169669A (en) * 2018-03-26 2019-10-03 キヤノン株式会社 Electronic module and imaging system

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