JPS5731081A - Vector processor - Google Patents
Vector processorInfo
- Publication number
- JPS5731081A JPS5731081A JP10590080A JP10590080A JPS5731081A JP S5731081 A JPS5731081 A JP S5731081A JP 10590080 A JP10590080 A JP 10590080A JP 10590080 A JP10590080 A JP 10590080A JP S5731081 A JPS5731081 A JP S5731081A
- Authority
- JP
- Japan
- Prior art keywords
- access
- bank
- nvr
- operating part
- pipeline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To control with less idle time by providing a bank controlling part that controls access in common against a pipeline device and by specifying timing with which the pipeline device accesses a vector register. CONSTITUTION:Element data are stored in a plurality of vector registers #0VR- #nVR so that said data are dispersed in an interleaved plurality bank units 1-0- 1-7 and each element of the registers #0VR-#nVR is accessed by one pipeline operating part 5 or a plurality of them and a memory pipeline 2. A bank slot that indicates timing with which the operating part 5 and the line 2 access each of units 1-0-1-7 is controlled in a bank controlling part 7. Furhter, when the operating part 5 and the line 2 access the registes #0VR-#nVR, a bank slot signal for access is sent to the controlling part 7, and a response signal as to whether it is possible or not against the signal from the controlling part 7 is sent to the operating part 5 and the line 2, thereby specifying timing of access.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10590080A JPS5731081A (en) | 1980-07-31 | 1980-07-31 | Vector processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10590080A JPS5731081A (en) | 1980-07-31 | 1980-07-31 | Vector processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5731081A true JPS5731081A (en) | 1982-02-19 |
Family
ID=14419751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10590080A Pending JPS5731081A (en) | 1980-07-31 | 1980-07-31 | Vector processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5731081A (en) |
-
1980
- 1980-07-31 JP JP10590080A patent/JPS5731081A/en active Pending
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